Part Number Logic Family

74ALS00 Advanced low-power Schottky TTL

74F00 Fast TTL

CMOS 74HC00 High-speed CMOS

74HCT00 High-speed CMOS (TTL-compatible inputs)

74LVX00 Low-voltage CMOS

H

H

L

_

_

L

VIL

_

_

_

_

_

FIGURE 11.1

Input/Output Voltage Parameters

H

H

L

IOL

L

IIL

IOH

Input/Output Current Parameters

The voltages and currents are designated with two subscripts, one that designates an

input or output and another that indicates the logic level. For example, VOL is the voltage at

the gate output when the output is in the logic LOW state. IIL is the input current when the

input is in the LOW state.

These voltages and currents are specified in manufacturers’ published data sheets,

which are usually available in print form in a data book or in an electronic format, such as

Portable Document Format (pdf) on a CD or internet site.

Figure 11.3 shows a data sheet for a 74LS00 NAND gate, which also shows parameter

values for a 54LS00 device. A 54-series device is manufactured to military specifications,

which require a high range of environmental operating conditions.A74-series device is suitable

for general or commercial use.We will limit ourselves to the 74-series devices.

The voltage and current parameters indicated in Figures 11.1 and 11.2 are all shown in

the 74LS00 data sheet. Some parameters are shown as typical values, as well as maximum or

minimum. Typical values should be considered “information only” as device manufacturers

74LS00 Data (1 of 2) Reprinted with permission of Motorola.

VCC Supply Voltage 54

74

4.5

5.0

5.5

V

TA Operating Ambient Temperature Range 54

–55

25

25

70

C

IOL Output Current — Low 54

74

4.0

mA

SN54/74LS00

CERAMIC

PLASTIC

14

1

1

ORDERING INFORMATION

SN54LSXXJ Ceramic

SN74LSXXN Plastic

SN74LSXXD SOIC

14

1

SOIC

14 13

12 11 10 9

VCC

8

7

• ESD > 3500 Volts

do not guarantee these values. An exception to this would be the supply voltage, VCC, whose

typical value is simply indicated as the average of maximum and minimum values.

Note that IIH and IIL are shown in Figure 11.2 as flowing in opposite directions, as are

leaving the gate is shown as having a negative value. The reason for these current directions

will become apparent when we examine the internal circuits of the gates later in the chapter.

❘❙❚ EXAMPLE 11.1 What is the maximum value of VOL for a 74LS00 NAND gate when the output current is at

its maximum value?

Solution When the output is in the LOW state, the output current is given by IOL,

which has a maximum value of 8 mA. The output voltage, VOL, is specified for a value of

4 mA and for 8 mA. Since the output condition is specified for maximum IOL (8 mA),

then VOL _ 0.5 V.

❘❙❚

FIGURE 11.3

74LS00 Data (2 of 2) Reprinted with permission of Motorola.

VIH Input HIGH Voltage 2.0 V

Guaranteed Input HIGH Voltage for

All Inputs

VIL Input LOW Voltage

54 0.7

Guaranteed Input LOW Voltage for

74 0.8

g

All Inputs

VOH Output HIGH Voltage

54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH

74 2.7 3.5 V

CC OH IN IH

or VIL per Truth Table

VOL Output LOW Voltage

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VIN = VIL or VIH

74 0.35 0.5 V IOL = 8.0 mA

per Truth Table

IIH Input HIGH Current

20 A VCC = MAX, VIN = 2.7 V

0.1 mA VCC = MAX, VIN = 7.0 V

IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V

IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX

ICC

Power Supply Current

Total, Output LOW 4.4

CC

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

tPLH Turn-Off Delay, Input to Output 9.0 15 ns VCC = 5.0 V

tPHL Turn-On Delay, Input to Output 10 15 ns

CC

CL = 15 pF

The 74XX00 NAND gate data is sufficient to represent any logic functions having

“normal” output current within its particular logic family. This data can be used for most

gate or flip-flop circuits within the family. Some specialized devices with higher-current

outputs (e.g., 74XX244 octal tristate buffers) have a different set of electrical characteristics

within their family.

In the following sections of the chapter, we will use a NAND gate from each of

three device families (74LS00, 74HC00A, and 74HCT00A) for illustrating the general

principles of the various electrical characteristics. Devices from other families will also

be used in examples and problems. Data sheets for the various devices are included in

Appendix C.

❘❙❚ SECTION 11.1 REVIEW PROBLEM

11.1 What are the maximum values of voltage and current we can expect at the output of

a 74LS00 NAND gate when both inputs are LOW?

Propagation delay occurs because the output of a logic gate or flip-flop cannot respond

instantaneously to changes at its input. There is a short delay, on the order of several

nanoseconds, between input change and output response. This is largely due to the charging

and discharging of capacitances inherent in the switching transistors of the gate or flipflop.

Figure 11.4 shows propagation delay in two gates: a 74XX00 NAND gate and a

74XX08 AND gate. Each gate has an identical input waveform, a LOW-HIGH-LOW

pulse. After each input transition, the output changes after a short delay, tp.

K E Y T E R M S

FIGURE 11.4

Propagation Delay in NAND and AND Gates

Two delays are shown for each gate: tpLH and tpHL. The LH and HL subscripts show

the direction of change at the gate output; LH indicates that the output goes from LOW to

HIGH, and HL shows the output changing from HIGH to LOW.

Propagation delay is the time between input and output voltages passing through a

standard reference value. The reference voltage for standard TTL is 1.5 V. LSTTL and

CMOS have different reference voltages, as follows.

LSTTL: Time from 1.3 V at input to 1.3 V at output.

Other TTL: Time from 1.5 V at input to 1.5 V at output.

CMOS: Time from 50% of maximum input to 50% of maximum output.

❘❙❚ EXAMPLE 11.2 Use the data sheet in Figure 11.3, as well as those in Appendix C, to find the maximum

propagation delays for each of the following gates: 74LS00 (quadruple 2-input NAND),

74LS02 (quadruple 2-input NOR), 74LS08 (quadruple 2-input AND), and 74LS32

(quadruple 2-input OR).

N O T E

Table 11.2 shows the variation of propagation delay among logic gates of the same

family (74LS TTL). Since each logic function has a different circuit, its propagation delay

will differ from those of gates with different functions.

❘❙❚ EXAMPLE 11.3 Use data sheets to find the maximum propagation delays for each of the following logic

gates: 74F00, 74AS00, 74ALS00, 74HC00, and 74HCT00.

*Temperature range (74F00): 0°C to 70°C.

**VCC _ 4.5 V, temperature range (74HC00): _55°C to 25°C.

***VCC _ 5 V, temperature range (74HCT00): _55°C to 25°C.

As indicated by the notes for Table 11.3, propagation delay (and other parameters)

vary with certain operating conditions, such as ambient temperature and power supply

voltage. Always make sure that the operating conditions are correctly specified when looking

up a data sheet parameter.

❘❙❚

All gates in Example 11.3 have the same logic function (2-input NAND), but different

TTL gate (74AS00), since it is the fastest?” The main reason is that it has the highest

power dissipation of the gates shown. We wouldn’t know this without looking

up other specs on the data sheet. (We will learn how to do this later in the chapter.) Thus,

it is important to make design decisions based on complete information, not just one

parameter.

Propagation Delay in Logic Circuits

A circuit consisting of two or more gates or flip-flops has a propagation delay that is the

sum of delays in the input-to-output path. Delays in gates that do not affect the circuit

output are disregarded. Figure 11.5 shows how propagation delay works in a simple logic

circuit consisting of a 74HC08 AND gate and a 74HC32 OR gate. Changes at inputs A and

the sum of tp1 and tp2. A change at input C must pass only through gate 2. The circuit delay

resulting from this change is only tp2.

FIGURE 11.5

Propagation Delays in a Logic Gate Circuit

The timing diagram in Figure 11.5 shows the changes at inputs A, B, and C and the resulting

transitions at all gate outputs.

Assume VCC _ 4.5 V and temperature range is _55°C to 25°C.

1. When A goes LOW, AB, the output of gate 1, also goes LOW after a maximum delay of

delay: tp _ tpHL1 _ tpHL2 _ 15 ns _ 15 ns _ 30 ns, max.

2. The HIGH-to-LOW transition at input B has no effect, since there is no difference between

0 _ 1 and 0 _ 0. AB is already LOW.

3. The LOW-to-HIGH transition at input C makes Y go HIGH after a maximum delay of

tpLH2 _ 15 ns.

❘❙❚ SECTION 11.2 REVIEW PROBLEM

11.2 Assume the gates in Figure 11.5 are replaced by a 74LS08 AND gate and a 74LS32

OR gate. Repeat the calculations of for the propagation delays if the waveforms of

Figure 11.5 are applied to the circuit. The data sheets for the 74LS08 and 74LS32 are

found in Appendix C.

without possible logic errors.

flows out of the terminal.

into the terminal.

We have assumed that logic gates are able to drive any number of other logic gates. Since

gates are electrical devices with finite current-driving capabilities, this is obviously not the

case. The number of gates (“loads”) a logic gate can drive is referred to as its fanout.

Fanout is simply an application of Kirchhoff’s current law: The algebraic sum of

currents at a node must be zero. Thus, the fanout of a logic gate is limited by:

a. The maximum current its output can supply safely in a given logic state (IOH or

IOL), and

b. The current requirements of the load to which it is connected (IIH or IIL).

Figure 11.6 shows the fanout of an AND gate when its output is in the HIGH and

LOW states. The AND gate, or driving gate, supplies current to the inputs of the other four

gates, which are called the load gates.

Each load gate requires a fixed amount of input current, depending on which state it is

in. The sum of these input currents equals the current supplied by the driving gate. The

N O T E

Driving Gates and Load Gates

fanout is determined by the amount of current the driving gate can supply without damaging

its output circuit.

The input and output currents of a gate are established by its internal circuitry. These

values are usually the same for two gates in the same family, since the input and output circuitry

of a gate is common to all members of the family. Exceptions may occur when the

output of a particular gate, such as the 74XX244 octal three-state buffer, has additional output

buffering or an input of a gate such as a 74LS86 Exclusive OR is equivalent to more

than one input load.

❘❙❚ EXAMPLE 11.4 The gates in Figure 11.7a and b are 74LS00 NAND gates. Determine the output current of

the driving gate in each figure.

H

H

L

IIL

L

IOH

IIH

Example 11.4

Output Current due to One

Load Gate

values of IIH given in the data sheet. Choose the one for the condition VIN _ 2.7 V, which

is the minimum output voltage of a driving gate in the HIGH state (VOH). The other value

is not appropriate since a gate will never have a 7 V output, as specified in the condition, if

its supply voltage is 5 V.)

Since the driving gate is driving one load, its output current is the same as the input

current of the load gate. Therefore, the driving gate output currents are given by IOL _ 0.4

mA (positive, since it is entering the driving gate output) and IOH _ _20 _A (negative,

since it is leaving the driving gate output).

❘❙❚ EXAMPLE 11.5 Determine the output current of the driving gate in each of Figures 11.8a and b if the gates

are all 74LS00 NAND gates.

H

H

L

IIL

L

L

H

IIH

Example 11.5

Output Current due to Two Load

Gates

gate output current will be twice the load gate input current.

❘❙❚

number of load gates is the maximum that can be driven by the driving gate. This is the

condition used to calculate fanout.

H

H

L 1

nL

IIL

IIL

L

L

H 1

nH

IIH

IIH

Output Current to Fanout Calculation

If the load gates each represent the same load, then by Kirchhoff’s current law (KCL):

IOL_ IIL1 _ IIL2 _ … IILnL _ nL IIL

and IOH _ IIH1 _ IIH2 _ … _ IIHnH _ nH IIH

The fanout of the driving gate in the LOW and HIGH states can be calculated as:

nL_

IOL

IIL

and nH_

By convention, current entering a gate (IIH, IOL) is denoted as positive, and current leaving

a gate (IIL, IOH) is denoted as negative. When current is leaving a gate, we say the gate is

sourcing current. When current is entering a gate, we say the gate is sinking current.

Note that the output of a gate does not always source current, nor does an input always

sink current. The current direction changes for the HIGH and LOW states at the same terminal.

The reason for this will become apparent when we study the circuitry of logic gate

inputs and outputs.

508 C H A P T E R 1 1 • Logic Gate Circuitry

❘❙❚ EXAMPLE 11.6 How many 74LS00 inputs can a 74LS00 NAND gate drive? (that is, what is the fanout of

a 74LS00 NAND gate?)

Solution We must consider the following cases:

a. When the output of the driving gate is LOW

b. When the output of the driving gate is HIGH

Output LOW:

IOL _ 8 mA (sinking)

IIL _ _0.4 mA (sourcing)

nL _ 8 mA/0.4 mA _ 20

Output HIGH:

IOH _ _0.4 mA (sourcing)

IIH _ 20 _A (sinking)

nH _ 0.4 mA/20 _A _ 20

Since nL _ nH, fanout is 20.

We disregard the negative sign in our calculations, since the input current of the load

gate and output current of the driving gate are actually in the same direction. For example,

even though IOH is leaving the driving gate (negative), IIH is entering the load gates (positive).

These currents flow in the same direction. If we include the minus sign in our calculation,

we get a negative value of fanout, which is meaningless.

❘❙❚

so. If the values of HIGH- and LOW-state fanout are different, the smallest value

must be used. For example, if a gate can drive four loads in the HIGH state or eight in the

LOW state, the fanout of the driving gate is four loads. If we attempt to drive eight loads,

we can’t guarantee enough driving current to supply all loads in both states.

If a gate from one logic family is used to drive gates from another logic family, we

must use the output parameters (IOL, IOH) for the driving gate and the input parameters (IIL,

IIH) for the load gates.

❘❙❚ EXAMPLE 11.7 Calculate the maximum number of Schottky TTL loads (74SXX series) that a 74LS86

XOR gate can drive.

Solution

Driving gate: 74LS86 IOH__0.4 mA,

Load gates: 74SXX IIH _ 50 _A,

Since nL _ nH, fanout _ nL _ 4.

❘❙❚

11.3 • Fanout 509

What happens if we load a gate output beyond its rated fanout? Adding more load

gates will do this by increasing the value of IOL beyond its maximum rating. If enough load

is added, the output of the driving gate might be destroyed by the heat generated by the excess

current. More likely, the performance of the driving gate will be degraded.

Figure 11.10 shows the relationship between output voltage and current for a 74LS00

and a 74F00 NAND gate. Figure 11.10a shows that the output voltage (LOW state) increases

with increasing sink current. Figure 11.10b indicates a decrease in HIGH state output

voltage with an increase of source current.

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