Value of External Pull-up Resistor

The value of the pull-up resistor required by an open-collector circuit is calculated using

manufacturer’s specifications and the basic principles of circuit theory: Kirchhoff’s voltage

and current laws (KVL and KCL) and Ohm’s law.

Figure 11.33 shows the circuit model for calculating the value of Rext. It accounts for

the current requirements of the loads, the LOW-state output voltage, and current-sinking

capacity of the open-collector gate.

FIGURE 11.31

NAND Gates in Wired-AND Connection

A Y

74LS07

Vcc _ 5 V _ 24 V

Example 11.14

74LS07 High-Current Driver

530 C H A P T E R 1 1 • Logic Gate Circuitry

The main rule in resistor selection is to keep the sum of currents into the open-collector

output to less than the maximum rated value of IOL.

IOL _ IR _ nIIL

IR _ (VCC _ VOL/Rext

❘❙❚ EXAMPLE 11.15 Calculate the minimum value of the pull-up resistor for a 74LS05 inverter if the circuit drives

ten 74LS00 NAND gate inputs.

Solution

From 74LS00 specs: IIL _ 0.4 mA

For 10 gates: nIIL _ 10IIL _ 4 mA

From 74LS05 specs: IOL _ 8 mA

_ 8 mA _ 4 mA

_ 4 mA

For IOL _ 8 mA, VOL _ 0.5 V

_ (5 V _ 0.5 V)/4 mA

_ 4.5 V/4 mA _ 1.125 k_

Use a 1.2-k_ or 1.5-k_ standard value resistor.

❘❙❚

❘❙❚ SECTION 11.7B REVIEW PROBLEM

drives one input of a 74LS00 NAND gate. What is the minimum standard value of

this resistor?

N O T E

Circuit Model for Pull-up Resistor Calculation

Totem Pole Outputs

only one of which is active at any time.

HIGH-state output transistors of a totem pole output are always in opposite phase

(i.e., one ON, one OFF).

Figure 11.34 shows one gate of a 7400 quadruple 2-input NAND with totem pole outputs.

The circuit is the same as that for a 7401 open-collector NAND except for a transistor, resistor,

and diode, which make up the HIGH-state output circuitry of the NAND gate.

K E Y T E R M S

FIGURE 11.34

NAND Gate With Totem Pole Output

The totem pole output, shown in Figure 11.34b, has separate transistors to switch the

output to the HIGH state (Q4) and the LOW state (Q3). These transistors are switched by

flow simultaneously.

The portion of the circuit consisting of Q4, D3, and the 130-_ resistor replaces the external

pull-up resistor required by the open-collector TTL output. Since the HIGH state is

switched by its own transistor, we say that the circuit has an active pull-up.

The main advantage of the totem pole output over the open collector is that it can

change states faster. The external pull-up resistance needed in an open-collector circuit

slows down the output switching by contributing to the RC time constant of the output. The

HIGH-state transistor circuit, with its relatively low output impedance, reduces this time

constant and thus improves switching speed.

Figure 11.35 shows the operation of the 7400 NAND gate for HIGH and LOW input

conditions.

HIGH Input. When both inputs are HIGH, there is no low-impedance base-emitter current

path in Q1. The base-collector junction of Q1 acts as a forward-biased diode. Base current

flows in Q2, saturating the transistor. Sufficient current flows to Q3 to saturate it. Y is

connected to ground, via the collector-emitter path of Q3. The output is LOW.

operates the same way if A or both A and B are LOW.

In this condition, a low-impedance path to ground is established through one of the

base-emitter junctions of Q1. This pulls the base of Q2 LOW, causing it to be in cutoff

NAND Gate Operation

mode. No current flows through the collector-emitter path of Q2, so no base current flows

in Q3; it is also cut off.

Current flows through the 1.6-k_ resistor to the base of Q4, turning it ON. This connects

the output, via Q4, D3, and the 130-_ resistor, to VCC. The output is HIGH.

Q4 will not turn ON when Q3 is ON. We can find out why by calculating VBE4 _ VD3.

For Q4 to conduct, two pn junctions (D3 and the base-emitter junction of Q4) must be forward-

biased. Thus, (VBE4 _ VD3) must be greater than 0.6 V _ 0.6 V _ 1.2 V.

VBE4 _ VD3 _ VB4 _ VCE3

We can calculate VB4 by adding up voltage drops, as follows:

The difference between these voltages is:

This is insufficient to forward-bias BE4 and D3. Q4 stays OFF.

Without D3 in the circuit,

VBE4 _ (VCE2 _ VBE3) _ VCE3

_ (0.2 V _ 0.7 V) _ 0.2 V

_ 0.7 V

This is sufficient to saturate Q4, even when Q3 is ON. The diode is therefore necessary

of a bipolar transistor before it can turn off.

A totem pole output is an inherently noisy circuit. Noise is generated on the supply voltage

line when the output switches from LOW to HIGH.

When the output is in a steady HIGH or LOW state, Q3 and Q4 are always in opposite

phase. The design of the totem pole output is such that when Q3 is ON, it is saturated, but

when Q4 is ON, it operates in the transistor’s active, or linear, region.

A saturated transistor takes longer to shut off than an unsaturated one due to storage

Thus, Q3 takes longer to turn off than Q4.

When a totem pole output is LOW, Q3 is ON and Q4 is OFF. When the output changes

state, Q4 turns ON before Q3 can turn OFF, due to the storage time of Q3. For a few

nanoseconds, both transistors are ON. This condition momentarily shorts VCC to ground,

causing a surge of supply current, as shown in Figure 11.36.

The inductance of the power line produces a corresponding spike proportional to the

instantaneous rate of change of the supply current (v _ L di/dt, where L is the power line

inductance and di/dt is the instantaneous rate of change of supply current).

These spikes on the supply voltage line can cause real problems, especially in synchronous

circuits. They often cause erroneous switching that is nearly impossible to troubleshoot.

The best cure for such problems is prevention.

K E Y T E R M

N O T E

Figure 11.37 shows the addition of a decoupling capacitor to a totem pole output to

eliminate switching spikes. A low-inductance capacitor of about 0.1 _F is placed between

the VCC and ground pins of the chip to be decoupled. This capacitor offsets the power line

inductance and acts as a low-impedance path to ground for high-frequency noise (i.e.,

spikes). Since a capacitor is an open circuit for low frequencies, the normal DC supply

voltage is not shorted out.

FIGURE 11.36

Spikes on Power Line During LOW-to-HIGH Transition of Totem Pole Output

Decoupling the Power Supply

It is important that the capacitor be placed physically close to the decoupled chip.

Inductance of the power line accumulates with distance, and if the capacitor is far

away from the chip (say, at the end of the circuit board), the decoupling effect of

the capacitor is lost.

N O T E

Placement of Decoupling Capacitor (Low-Frequency Designs)

It is not necessary to decouple every chip on a circuit board for designs operating at

relatively low frequencies (_1 MHz). In such cases, one capacitor for every two ICs is

enough. The capacitor should be connected between VCC and ground of the same chip, as

shown in Figure 11.38.

For high-frequency designs, use one capacitor per IC, as shown in Figure 11.39. Connect

directly to power and ground traces on a printed circuit board, as close as possible to

the chip being decoupled.

Connection of Totem Pole Outputs

Totem pole outputs must never be connected together. As shown in Figure 11.40, the problem

occurs when two connected outputs are in opposite states.

The active pull-up consisting of Q4, D3, and the 130-_ resistor is designed to supply

current to about 10 TTL inputs, each having a large input impedance. It will not withstand

the current that flows when the output is forced to ground through the LOW output transistor

of another gate.

Under this condition about 30 to 55 mA will flow through Q4A and Q3B. This exceeds

the ratings of the outputs in both the HIGH and LOW state and will cause damage to the

outputs over time. The outputs will probably withstand this sort of abuse for several minutes,

but eventually will be damaged.

FIGURE 11.39

Placement of Decoupling

Capacitors (High-Frequency

Designs)

❘❙❚ SECTION 11.7C REVIEW PROBLEM

11.9 A totem pole output is likely to be damaged when shorted to ground. Why?

Tristate Gates

and a high-impedance state, in which the output acts as an open circuit.

Figure 11.41 shows the circuits of two TTL inverters with tristate outputs. In addition to the

usual binary states of HIGH and LOW, the output of the tristate inverter can also be in a

“high-impedance” (Hi-Z) state. This state occurs when both Q3 and Q4 are OFF. The electrical

effect is to produce an open circuit at the output, which is neither HIGH nor LOW.

The output of a tristate gate combines advantages of a totem pole output and an opencollector

output. Like the totem pole output, it has an active pull-up with lower output impedance

and faster switching than an open collector. Like the open collector, we can connect

several outputs together, provided only one output is active at a time.

Input G, the “gating” or “enable” input, controls the gate. When G is active, the gate

acts as an ordinary inverter. When inactive, the gate is in the high-impedance state. Table

11.6 summarizes the operation of the tristate inverters in Figure 11.41.

The tristate inverter in Figure 11.41a is enabled by a HIGH at the G input. The circuit

is the same as a 7400 NAND gate with two exceptions: (1) an extra diode goes from the

base of Q4 to G, and (2) G connects directly to one of the emitters of Q1.

When G _ 0, Q1 acts as though there was a LOW at a NAND gate input. In a 7400

NAND circuit, this causes Q2 and Q3 to be in cutoff mode.

Due to the opposite states of the emitter and collector in Q2, Q4 would normally be

ON. Instead, the LOW at G pulls the base of Q4 LOW through the extra diode. Thus, both

When G _ 1, the G emitter of Q1 acts like a HIGH NAND input. By the enable/

inhibit rules of a NAND gate, Y _ _A. The additional diode prevents the HIGH at G from

activating Q4.

The circuit in Figure 11.41b works the same way, except for the opposite sense of the

activating input. This opposite active level is achieved by using an open-collector inverter,

consisting of Q5, Q6, and Q7, at input _G.

K E Y T E R M

Totem Poles Connected Together

Tristate Inverters

Inverters

0 0 Hi-Z 0 0 1

0 1 Hi-Z 0 1 0

1 0 1 1 0 Hi-Z

1 1 0 1 1 Hi-Z

538 C H A P T E R 1 1 • Logic Gate Circuitry

❘❙❚ SECTION 11.7D REVIEW PROBLEM

11.10 Why is the diode from the base of Q4 necessary in the tristate inverters in Figure

11.41?

Other TTL gates are similar to the NAND and inverter gates we have already examined. A

significant variation is the OR/NOR circuit, which has a different input configuration than

the AND/NAND/inverter type gates.

Figure 11.42 shows one gate of a 7402 quadruple 2-input NOR gate package. The difference

between this gate and the 7400 NAND gate is the structure of the inputs. The NOR

gate does not use the multiple-emitter transistor, but rather an individual transistor (Q1 or

emitter and collector-to-collector.

7402 NOR Gate Circuit

If either Q3 or Q4 is enabled by a HIGH at its corresponding input, it will turn on Q5,

making the output LOW.

If both gate inputs are LOW, both Q3 and Q4 are in cutoff mode, and so is Q5. The output

is HIGH through Q6.

Table 11.7 shows the truth table and the states of the transistors for this gate. It is not

strictly correct to refer to Q1 and Q2 as being ON or OFF, since there is current flowing in

these transistors regardless of whether the inputs are HIGH or LOW. Let us define the ON

11.8 • Internal Circuitry of MOS Gates 539

state of an input transistor as the condition where the base-emitter junction is conducting

(LOW input). If the base-collector junction conducts, we will consider the transistor OFF

(HIGH input).

It may not be obvious why we would choose to study NAND and NOR gates before AND

and OR. After all, AND and OR are the more basic logic functions.

Electrically, it works the other way around. The simplest TTL circuit is the NAND/inverter,

followed by the NOR. AND and OR gates are more complex since they are based on

the NAND and NOR and require an extra inverter stage.

0 0 ON ON OFF OFF OFF ON 1

0 1 ON OFF OFF ON ON OFF 0

1 0 OFF ON ON OFF ON OFF 0

1 1 OFF OFF ON ON ON OFF 0

FIGURE 11.43

7408 AND Gate

Figure 11.43 shows the circuit of a 7408 AND gate, and Figure 11.44 shows a 7432

TTL OR gate circuit. Each of these gates is like its NAND/NOR counterpart, except for an

additional inverter, implemented by Q3 in the AND gate and Q5 in the OR gate.

Tables 11.8 and 11.9 show the transistor function and truth table for each gate. In

keeping with the convention established for the NOR function table, an input transistor

with a conducting base-emitter junction is considered ON.

❘❙❚ SECTION 11.7E REVIEW PROBLEM

11.11 Why are noninverting gates more complex than inverting gates?

11.8 Internal Circuitry of MOS Gates

three terminals—gate, source, and drain—which are analogous to the base, emitter,

and collector of a bipolar junction transistor.

K E Y T E R M S

7432 OR Gate

0 0 ON ON OFF OFF OFF ON ON OFF 0

0 1 ON OFF OFF ON ON OFF OFF ON 1

1 0 OFF ON ON OFF ON OFF OFF ON 1

1 1 OFF OFF ON ON ON OFF OFF ON 1

Table 11.8 7408 AND Function and Truth Table

A B Q1

Q2 Q3 Q4 Q5 Q6 Y

0 0 ON OFF OFF ON ON OFF 0

0 1 ON OFF OFF ON ON OFF 0

1 0 ON OFF OFF ON ON OFF 0

1 1 OFF ON ON OFF OFF ON 1

11.8 • Internal Circuitry of MOS Gates 541

Enhancement-mode MOSFET A MOSFET that creates a conduction path (a

channel) between its drain and source terminals when the voltage between gate and

source exceeds a specified threshold level.

Substrate The foundation of n- or p-type silicon on which an integrated circuit is

built.

with n-type drain and source regions. An n-type channel is created in the psubstrate

during conduction.

p-channel enhancement-mode MOSFET A MOSFET built on an n-type substrate

with p-type drain and source regions. During conduction, a p-type channel is

created in the n-substrate.

CMOS A logic family based on the switching of n- and p-channel (“complementary”)

enhancement-mode MOSFETs.

All the logic circuits we have examined so far have been based on the switching of bipolar

junction transistors. Another major logic family, CMOS, is based on the switching of

metal-oxide-semiconductor field effect transistors, or MOSFETS.

There are two major types of MOSFETs, called depletion-mode and enhancementmode

type used in the manufacture of digital ICs. Details of the differences between depletionand

enhancement-mode transistors can be found in any good textbook on electronic devices.

MOSFETs can be categorized in another way: as n-channel and p-channel devices,

much as bipolar transistors are classified as NPN or PNP.

CMOS logic is constructed from both n- and p-channel MOSFETs. CMOS (“Complementary

MOS”) refers to the opposite, or complementary, operation of n- and p-channel

transistors.

MOSFET Structure

Figure 11.45 shows the structure and symbol of an n-channel enhancement-mode MOSFET

in an integrated circuit. The device is built on a substrate of p-type silicon, which has

a deficiency of electrons in its structure. The drain and source regions are “wells” of n-type

silicon, which has an excess of electrons. The drain and source are roughly equivalent to

the emitter and collector of a bipolar transistor.

n-Channel MOSFET

The substrate is shown as a terminal with an arrow. The arrow points in for an nchannel

device and out for a p-channel device. In nearly all cases, the substrate is shorted

to the source terminal. (Some exceptions to this general rule will be examined when we

look at circuits of CMOS gates.)

The gate terminal is similar to the base of a bipolar transistor in that it controls the flow

of current between the drain and source. The difference is that a MOSFET uses gate voltage

to control drain current, whereas a bipolar transistor uses base current to control collector

current.

The gate consists of an insulating layer of silicon dioxide (SiO2) and a layer of metal

over the substrate between the drain and source. This gate structure is what gives the MOSFET

its name (metal-oxide-semiconductor field effect transistor).

The oxide layer of the gate structure is subject to damage if excessive voltage

(greater than about 100 V) is applied. This especially includes static electricity, or

electrostatic discharge (ESD). There are standard precautions for working with

MOS devices that should be followed carefully.

Most important are ensuring that MOS devices are stored in antistatic or conducting

material, that work surfaces are not likely to generate static, that unused inputs

are not left open or floating, that you avoid touching the pins of a MOS device,

and that if you must handle a MOS IC, you discharge any static on your person before

touching it.

A conductive wrist strap with a high series resistance to ground (about 1 M_)

is often worn to reduce static. The high resistance protects the operator from shock

injury in the event of a short circuit.

A list of handling precautions is included in Appendix D.

❘❙❚ SECTION 11.8A REVIEW PROBLEM

11.12 Why are MOSFET circuits particularly susceptible to static damage?

Bias Requirement for MOS Transistors

ON, it acts like a relatively low resistance, or “ohmically.”

when an enhancement-mode n-channel MOSFET is biased ON. Also referred to as

the channel.