Chapter 1 Basic Principles of Digital Systems outlin e 1

Metal-Gate CMOS Circuits

The 74HCTNN devices are designed to be directly compatible with LSTTL devices,

and thus have LSTTL-equivalent inputs and CMOS-equivalent outputs.

74HCUNN devices have no output buffers, like the 4000 UB-series standard CMOS

devices. The 74HCU devices are used, as are the 4000UB devices, for linear applications

such as oscillators and multivibrators.

Table 11.15 shows the relative performance of the various CMOS families. As in TTL,

the 2-input NAND gate is used as the standard, except for the HCU family, where this gate

is not available. The quiescent speed-power product of all CMOS families is much smaller

than that of any TTL family. The high-speed CMOS families have propagation delays

comparable to those of LSTTL.

The power dissipation of a CMOS device increases directly with frequency. The

speed-power product also goes up with higher frequencies.

Table 11.15 shows CMOS speed-power product for a switching speed of 1 MHz. At

these speeds, B-series CMOS has no advantage over the common TTL families in terms of

its efficiency. It still has the edge on TTL with respect to noise immunity and power supply

flexibility.

❘❙❚ SECTION 11.9 REVIEW PROBLEM

11.14 Assuming that power dissipation of a 74HC00A NAND gate is directly proportional

to its switching frequency, what is the speed-power product of the gate at 2 MHz, 5

MHz, and 10 MHz?

Table 11.15 CMOS Speed and Power Specifications

Advanced High-Speed

Metal-Gate CMOS High-Speed CMOS CMOS Low-Voltage CMOS

4011B 4011UB 74HC00A 74HCT00A 74HCU04 74VHC00 74VHCT00 74LVX00 74LCX00

tpLH, tpHL 250 ns 180 ns 15 ns 19 ns 14 ns 5.5 ns 6.9 ns 6.2 ns 5.2 ns

IDD or ICC 0.25 _A 0.25_A 0.25 _A 0.25 _A 0.17 _A 0.5 _A 0.5 _A 0.5 _A 0.25 _A

VDD or VCC 5.0 V 5.0 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 3.3 V 3.3 V

PD (1 MHz) 1.5 mW 1.5 mW 446 _W 304 _W 303 _W 385 _W 385 _W 208 _W 272 _W

Speed-power 0.31 pJ 0.23 pJ 0.017 pJ 0.021 pJ 0.011 pJ 0.012 pJ 0.015 pJ 0.010 pJ 0.043 pJ

product

(quiescent)

Speed-power 375 pJ 270 pJ 6.68 pJ 5.77 pJ 4.25 pJ 2.12 pJ 2.65 pJ 1.29 pJ 1.42 pJ

product

(1 MHz)

S U M M A R Y

1. TTL (transistor-transistor logic) and CMOS (complementary

metal-oxide semiconductor) are two major logic families in

use today. TTL is constructed from bipolar junction transistors.

CMOS is made from metal-oxide-semiconductor field

effect transistors (MOSFETs).

2. The main CMOS advantages include low power consumption,

high noise immunity, and a flexibility in choosing a

power supply voltage.

3. The main advantages of TTL include relatively high switching

speed and an ability to drive loads with relatively high

current requirements.

4. TTL and high-speed CMOS logic families are alphabetically

designated by a part number having the form 74XXNN,

where XX is the family and NN is a numeric logic function

designator. (For example, 74HC00 and 74LS00 have the

same logic function, but are from different logic families.)

❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚

Devices from earlier CMOS families are designated by a part

number of the form 4NNNB or 4NNNUB.

5. Devices of the same logic family generally have the same

electrical characteristics.

6. Data such as input/output voltages and currents are specified

in manufacturers’ datasheets. Only the maximum or minimum

values of these parameters should be used as design information.

“Typical” values should be regarded as “information

only.”

result of an input change is called propagation delay.

8. Propagation delay is specified as tpLH when an output

changes from LOW to HIGH and tpHL when the output goes

from HIGH to LOW.

9. Propagation delay in a circuit is the sum of all delays in the

slowest input-to-output path. Gates whose outputs do not

change are ignored in the calculation.

10. Fanout is the maximum number of device inputs that can be

driven by the output of a logic device.

11. The actual value of output current in a driving gate is the sum

of all load currents, which are the input currents of the load

gates. For n loads,

IOL _ IIL1 _ IIL2 _ … _ IILnL _ nL IIL

and IOH _ IIH1 _ IIH2 _ … _ IIHnH _ nHIIH

12. The fanout of the driving gate in the LOW and HIGH states

can be calculated as:

O

IL

and nH _ _

O

IH

13. If the fanout is unequal for LOW and HIGH states, the

smaller value must be used.

14. If the fanout of a gate is exceeded, the output voltage of the

driving gate will drop if the output is HIGH and rise if

the output is LOW. This move away from the nominal value

degrades the general performance of the driving gate.

15. Power supply current (ICC), and therefore power dissipation

(PD), of a TTL device depends on the number of outputs

in the device that are HIGH or LOW. PD _ VCC ICC _

H_ ICCH _ _

L_

ICCL_ for a device with n outputs, nH of

which are HIGH and nL of which are LOW.

16. CMOS devices draw most current from the power supply

when its outputs are switching and very little when they are

static. Power dissipation of a high-speed CMOS device with

CC f _ _

At high frequencies (_1 MHz), the quiescent current

can be neglected.

17. Noise margin is a measure of the noise voltage that can be

tolerated by a logic device input. In the HIGH state, it is

given by VNH _ VOH _ VIH. In the LOW state, it is given by

noise margins than TTL.

18. When interfacing two devices from different logic families,

the driving gate must satisfy the voltage and current requirements

of the load gates.

19. Input current in a CMOS gate is very low, due to its high input

impedance. Thus, fanout is generally not a problem with

CMOS loads.

20. CMOS devices that have the same values of VIH and VIL as

TTL are considered to be TTL compatible, since they can be

driven directly by TTL drivers.

21. A 74HC or 74HCT device can drive 10 LSTTL loads directly.

To calculate fanout, we use the output currents for

which the driving gate output voltages are defined.

22. A 74LS device can drive one or more 74HC devices, provided

each 74HC input has a pull-up resistor (about 1 k_ to

10 k_) to supply sufficient voltage in the HIGH state.

23. A 74LS device can drive one or more 74HCT inputs directly.

24. Low-voltage CMOS (e.g., 74LVX or 74LCX) can be driven

directly by a TTL device if the CMOS device is operated

with a 3.3 V power supply. Noise margins are too small for a

low-voltage CMOS driver to drive TTL loads.

25. 74HC or 74HCT gates can be operated at a low value of VCC

(e.g., 3 volts) and interfaced to a higher-voltage driver by an

inverting or noninverting buffer, such as the 74HC4049 or

74HC4050. The interface buffer can tolerate relatively high

input voltages (up to 15 V) and, if it shares the same supply

voltage as the load gate, can provide correct input voltages to

the load.

26. A bipolar transistor with a grounded emitter acts as an inverter

or a digital switch. A HIGH at the base causes the transistor

to conduct, pulling the collector to near-ground potential.

If there is a pull-up resistor on the collector, there will be

a HIGH state at the collector when the base is LOW.

27. The simplest TTL input is a transistor with its base connected

to VCC through a resistor. It can be treated as two

diodes, back-to-back.

28. A TTL LOW input forward-biases the base-emitter junction

of the input transistor, supplying a path to ground for input

current.

of the input transistor and forward-biases its base-collector

junction. Input current in the HIGH state is restricted to reverse

leakage current through the base-emitter junction.

30. An open TTL input is equivalent to a HIGH, as it provides no

path to ground.

31. Some types of TTL gates, such as NAND, have multipleemitter

input transistors. Any one input LOW acts as a LOW

for the whole circuit.

32. Other TTL gates, such as NOR, have separate transistors for

each input. Any HIGH input acts as a HIGH for the whole

circuit.

switches on a path to ground (logic LOW) when it is turned

on. There is no separate internal circuit for a HIGH output.

This must be provided by an external pull-up resistor.

34. Open-collector outputs can be used to parallel outputs

(wired-AND), drive high-current loads, or interface to a circuit

with a different power supply voltage than the driving

gate.

LOW output and another that switches on for a HIGH output.

These output transistors are always in opposite states, except

briefly during times when the output is changing states.

36. Totem pole outputs generate noise spikes on the power line

of a circuit when they switch between logic states. These

Summary 557

558 C H A P T E R 1 1 • Logic Gate Circuitry

spikes can be amplified by inductance of the power line. Decoupling

capacitors placed close to each device help minimize

this problem.

37. TTL outputs should never be connected together, as they can

be damaged when the outputs are in opposite states. (Too

much output current flows.) The logic level under such conditions

is not certain.

38. Gates with tristate outputs can generate logic LOW, logic

HIGH, or high-impedance states. A high-impedance state is

like an open circuit or electrical disconnection of the gate

output from the circuit. In this state, both HIGH- and LOWstate

output transistors are off.

39. The operation of a tristate output is controlled by the state of

a control input. In one control state, the output is either

HIGH or LOW. In the opposite control state, the output is in

the high-impedance state.

40. CMOS (complementary MOS) devices are based on nchannel

and p-channel MOSFETs (metal-oxide-semiconductor

field effect transistors).

41. A MOSFET consists of a silicon substrate of a particular

type of silicon (e.g., p-type), embedded with wells of the opposite

type (e.g., n-type) that form the drain and source regions

of the MOSFET. A gate electrode can bias the substrate

to create a conduction channel between drain and source.

42. An n-channel enhancement mode MOSFET is biased on

when its gate voltage exceeds its source voltage by a given

amount called the threshold voltage.

43. A p-channel enhancement mode MOSFET is biased on when

its gate voltage is less than its source voltage by a given

amount called the threshold voltage.

44. An n-channel and p-channel MOSFET can be connected in

such a way that one of the pair of MOSFETs is always on

and one is always off. This connection is called a complementary

pair and forms the basis for CMOS logic.

45. Logic functions, such as NAND and NOR, can be implemented

with a complementary pair of MOSFETs for each input,

with the MOSFETs in series or parallel to VCC or

ground, as required.

46. Many TTL families have been designed to incorporate

Schottky barrier diodes, which limit the saturation of their

transistors, allowing faster internal and output switching

speeds.

47. Metal-gate CMOS has been superceded by high-speed

in faster switching and lower gate capacitance.

48. Speed-power product is a measure of the energy used by a

gate. More advanced logic families have smaller values of

speed-power product.

G L O S S A R Y

family based on the switching of n- and p-channel metal-oxidesemiconductor

field effect transistors (MOSFETs).

Cutoff mode The operating mode of a transistor when there is

no collector or drain current flowing and the path from collector

to emitter or drain to source is effectively an open circuit

Driving gate A gate whose output supplies current to the inputs

of other gates.

on bipolar transistors.

conduction path (a channel) between its drain and source terminals

when the voltage between gate and source exceeds a specified

threshold level.

of driving without possible logic errors.

a smaller device structure and thus higher speed than standard

(metal-gate) CMOS.

ICC Total supply current in a TTL or high-speed CMOS device.

ICCH TTL supply current with all outputs HIGH.

ICCL TTL supply current with all outputs LOW.

IDD CMOS supply current under static (nonswitching) conditions.

IIH Current measured at a device input when the input is

HIGH.

HIGH.

LOW.

and dynamic supply currents.

of another gate.

A MOSFET has three terminals—gate, source, and drain—

which are analogous to the base, emitter, and collector of a

bipolar junction transistor.

on a p-type substrate with n-type drain and source regions. An

radiation.

tolerate noise.

drain and source when an enhancement-mode n-channel MOSFET

is biased ON. Also referred to as the channel.

Ohmic region The MOSFET equivalent of saturation. When

a MOSFET is biased ON, it acts like a relatively low resistance,

or “ohmically.”

Open-collector output A TTL output where the collector of

the LOW-state output transistor is brought out directly to the

output pin. There is no built-in HIGH-state output circuitry

which allows two or more open collector outputs to be connected

without possible damage.

Glossary 559

built on an n-type substrate with p-type drain and source regions.

During conduction, a p-type channel is created in the

n-substrate.

Phase splitter A transistor in a TTL circuit which ensures that

the LOW- and HIGH-state output transistors of a totem pole output

are always in opposite phase (i.e., one ON, one OFF).

Power dissipation The electrical energy used by a logic circuit

in a specified period of time. Abbreviation: PD

circuit to change states after a change at one or more of its

inputs.

Saturation mode The operating mode of a bipolar transistor

when an increase in base current will not cause a further increase

in the collector current and the path from collector to

emitter is very nearly (but not quite) a short circuit. This is the

ON state of a transistor in a digital circuit.

Schottky barrier diode A specialized diode with a forward

drop of about _0.4 V.

across its base-collector junction, which prevents the transistor

from going into deep saturation.

Schottky TTL A series of unsaturated TTL logic families

based on Schottky transistors. Schottky TTL switches faster than

standard TTL due to decreased storage time in its transistors.

Sinking A terminal on a gate or flip-flop is sinking current

when the current flows into the terminal.

when the current flows out of the terminal.

calculated by multiplying its propagation delay by its

power dissipation. Unit: picojoule (pJ)

Storage time Time required to transport stored charge away

from the base region of a bipolar transistor before it can turn off.

integrated circuit is built.

gate and source of a MOSFET for the formation of the conducting

inversion layer (channel).

Totem pole output A type of TTL output with a HIGH and a

LOW output transistor, only one of which is active at any time.

from HIGH to LOW.

from LOW to HIGH.

HIGH, logic LOW, and a high-impedance state, in which the

output acts as an open circuit.

TTL Transistor-transistor logic. A logic family based on bipolar

transistors.

Usually implies voltage compatibility with TTL.

HIGH.

LOW.

HIGH.

LOW.

logic gates are wired together. The logical effect is the ANDing

of connected functions.

P R O B L E M S

CMOS, and ECL logic gates.

and CMOS devices. How do these measurements

differ?

11.3 Figure 11.65 shows the input and output waveforms of a

logic gate. Use the graph to calculate tpHL and tpLH.

1 in the following table. The inputs change to state 2, then

to state 3.

A B C

State 1 1 0 1

State 2 0 0 1

State 3 0 0 0

a. Draw a timing diagram that uses the above changes of

input state to illustrate the effect of propagation delay

in the circuit.

b. Calculate the maximum time it takes for the output

to change when the inputs change from state 1 to

state 2.

to change when the inputs change from state 2 to

state 3.

560 C H A P T E R 1 1 • Logic Gate Circuitry

11.5 Repeat Problem 11.4 , parts b and c, for a 74HC00

NAND and a 74HC02 NOR gate.

TTL loads (74LSNN series) that a 74S86 XOR gate can

drive.

11.7 What is the maximum number of 74S32 OR gates that a

74LS00 NAND gate can drive?

that a 74S32 OR gate can drive?

equivalent to the load presented by a 74LS00 NAND input.

Calculate the source and sink currents required from

the driving gate.