Chapter 1 Basic Principles of Digital Systems outlin e 1

MOSFET for the formation of the conducting inversion layer (channel).

When we studied the operation ofTTL gate circuits, we discovered that, for the most part, the

bipolar transistors in the gates operated either in the saturation or the cutoff regions. In MOStype

gates, we make use of two similar operating regions in the constituent MOSFETs:

1. The cutoff region is the same as that for a bipolar transistor. Under this condition, there

is a very high impedance between the drain and source terminals of the MOSFET.

2. The ohmic region is analogous to the saturation region of a bipolar transistor. In this

state, there is a relatively low resistance between the MOSFET’s drain and source.

The MOSFET switches between cutoff and ohmic regions when the voltage between

gate and source, VGS, is less than or greater than a value called the threshold voltage.

The abbreviation for this voltage is VGS(Th); its value is between 1 and 5 volts, typically 1.5V.

Figure 11.46 shows an n-channel MOSFET operating in the cutoff region. The gatesource

voltage, VGS is less than VGS(Th). There is no conduction between the drain and

source. The resistance, RDS(OFF), between drain and source is very large, typically in the

thousands of megohms.

K E Y T E R M S

N O T E

When the value of VGS increases and exceeds the threshold voltage, the MOSFET enters

the ohmic region. A conduction channel, called the n-type inversion layer, is created

in the p-substrate of the transistor, as shown in Figure 11.47. This layer is like an artificially

created region of n-type silicon, which allows conduction between the drain and

source, provided there is sufficient potential difference between them.

n-Channel MOSFET in Cutoff

Region

FIGURE 11.47

Channel Formation in an n-Channel MOSFET

Figure 11.48 shows a MOSFET operating in the ohmic region. RDS(ON), the equivalent

resistance of a MOSFET in the ohmic region, is typically around 500 _ to 2 k_. The drainsource

current, IDS, is determined by Ohm’s law: IDS _ VCC/RDS(ON).

FIGURE 11.48

n-Channel MOSFET in Ohmic

Region

544 C H A P T E R 1 1 • Logic Gate Circuitry

The operation of a p-channel MOSFET is similar, but with polarities reversed. If

voltage of _1.5 V. VGS _1.5 V turns ON an n-channel transistor; VGS _ _1.5 V

turns ON a p-channel device.

Figure 11.49 summarizes the bias requirements for n- and p-channel enhancementmode

MOSFETs.

FIGURE 11.49

Bias Requirements of n- and p-Channel MOSFETs

CMOS Inverter

Figure 11.50 shows the circuit of a CMOS inverter, which consists of one n-channel and

one p-channel MOSFET.

Recall the bias conditions of the two transistors:

ON when VGS VGS(Th) (e.g., VGS _ VCC)

OFF when VGS _ VGS(Th) (e.g., VGS _ 0 V)

p-channel: threshold voltage, VGS(Th) _ _1.5 V

ON when VGS _ VGS(Th) (e.g., VGS__VCC)

OFF when VGS VGS(Th) (e.g., VGS _ 0 V)

11.8 • Internal Circuitry of MOS Gates 545

The operation of the CMOS inverter, and any other CMOS gate, depends on arranging

the bias conditions of each complementary pair of transistors so that they are always in opposite

states. Whenever Q1 is ON, Q2 is OFF, and vice versa. Figure 11.51 shows how this

is accomplished.

Assume that a LOW input is at ground potential and that a HIGH input is equal to VCC.

CMOS Inverter

Operation of CMOS Inverter

When input A is LOW, the gate voltage of Q2 is the same as its source voltage; VGS2 _

0 and Q2 is OFF. This places a high-impedance path between output Y and ground. At the

same time, the gate voltage of Q1 is 0V and its source voltage is VCC; VGS1 _ VG1 _ VS1 _

0 _ VCC _ _VCC. (The p-channel transistor, Q1, is drawn “upside down” to make the

complementary pair symmetrical.) Q1 is ON, forming a low-impedance path from VDD to

the output Y. Output Y is HIGH.

When input A is HIGH, the gate-source voltage of the n-channel transistor is VCC,

causing Q2 to turn ON. The gate of Q1 is also at VCC. Since the source of the p-channel

transistor is at VCC, VGS1 _ VG1 _ VS1 _ VCC _ VCC _ 0 V; Q1 is OFF. This combination

creates a high impedance between VCC and output Y and a low-impedance path from output

Y to ground, as shown in Figure 15.51b. Output Y is LOW.

CMOS NAND/NOR Gates

CMOS NAND and NOR gates are constructed from complementary pairs of MOSFETs.

Each MOSFET pair has an n-channel transistor that is turned ON by a HIGH input and a

output to ground; the p-channel ones switch the output to VCC. NAND and NOR functions

are generated by arranging the MOSFET drain-source paths in series (AND) and parallel

(OR) configurations.

In Figure 11.52, we see the DeMorgan equivalent forms of a NAND gate. Each form

illustrates an aspect of NAND operation that can be described with a brief sentence and implemented

by a MOSFET circuit. The combination of forms describes the complete operation

of the device.

Figure 11.52a states that both NAND inputs must be HIGH to make the output LOW.

A logic HIGH activates an n-channel MOSFET. The gate output is switched to ground by

an n-channel MOSFET. Thus, the drain-source paths of two n-channel transistors must be

connected in series to make the output LOW under the stated conditions.

Figure 11.52b shows that the NAND output is HIGH if either input is LOW. A pchannel

transistor will turn ON when its gate is LOW and will switch a HIGH to the output.

A parallel combination of p-channel MOSFETs will satisfy these conditions.

FIGURE 11.52

NAND Functions of MOSFETs

The stated conditions are combined in the CMOS NAND circuit shown in Figure

11.53. Transistors Q1 and Q4 form a complementary pair, as do Q2 and Q3. When A and B

are both HIGH, Q1 and Q2 are both OFF, cutting off the connection between VCC and output

Y. Q3 and Q4 are both ON, supplying a low-impedance path from output Y to ground,

making the output LOW. This is shown in the partial truth table in Table 11.10.

When A is LOW and B is HIGH, Q1 is ON. This creates a path from VCC to output

Y. At the same time, Q4 is OFF. This cuts the Y-to-ground path through the n-channel

11.8 • Internal Circuitry of MOS Gates 547

MOSFETs; the series path from output to ground is broken. One parallel path from VCC to

output has been established. Output Y is HIGH.

The remaining input combinations also make the output HIGH, as shown in Table

11.11. They do so by breaking the n-channel path from output to ground and enabling one

or both p-channel paths from VCC to output.

Each MOSFET in a logic circuit must have its own independent substrate bias. This

ensures that the transistor will operate as expected when a logic HIGH or LOW is applied

to its gate.

Normally, the substrate of a MOSFET is shorted to its source terminal. If a MOSFET

source terminal is isolated from VCC or ground, the substrate must be biased separately. For

example, in the NAND gate in Figure 11.53, the substrate of Q3 connects directly to

ground.

NOR gates are similar to NANDs in construction. Figure 11.54 shows the DeMorgan

the gate operation.

Truth Table

1 1 OFF OFF ON ON 0

CMOS NAND Gate

and Truth Table

0 0 ON ON OFF OFF 1

0 1 ON OFF ON OFF 1

1 0 OFF ON OFF ON 1

NOR Functions of MOSFETs

When either input is HIGH, the output is LOW. This function is implemented by two

parallel n-channel MOSFETs. Both inputs must be LOW to make the output HIGH, which

implies a series connection of two p-channel transistors. The complete NOR gate circuit is

shown in Figure 11.55. (Note that the substrate of Q2 is connected directly to VCC to ensure

that it has its own bias voltage.)

CMOS NOR Gate

and Truth Table

0 0 ON ON OFF OFF 1

and Truth Table

0 1 ON OFF ON OFF 0

1 0 OFF ON OFF ON 0

1 1 OFF OFF ON ON 0

As was the case with the NAND circuit, transistors Q1 and Q4 form a complementary

MOSFET pair. Transistors Q2 and Q3 form the second pair.

When both inputs are LOW, both p-channel transistors are ON. This creates a lowimpedance

path from VCC to output Y. The n-channel transistors, Q3 and Q4, are both OFF.

This isolates the output from ground. Output Y is HIGH. Table 11.12 shows the MOSFET

states under this condition.

If either input is HIGH, one or both of the p-channel transistors will turn OFF. This action

breaks the path from VCC to output Y. The complementary n-channel transistor will

turn ON. This creates a low-impedance path from output Y to ground. Output Y is LOW.

Table 11.13 summarizes the possible input conditions and MOSFET states when the NOR

output is LOW.

11.8 • Internal Circuitry of MOS Gates 549

CMOS AND and OR Gates

Figures 11.56 and 11.57 show the circuits of CMOS AND and OR gates. The AND gate is

the same as the NAND circuit, except for the output inverter section constructed from Q5

and Q6. The OR gate is the same as the NOR with an output inverter section.

❘❙❚ SECTION 11.8B REVIEW PROBLEM

11.13 Why is the source of a p-channel MOSFET connected to VCC in a CMOS gate?

CMOS Transmission Gate

Figure 11.58 shows the circuit of a CMOS transmission gate. A CMOS transmission gate,

or analog switch, conducts in both directions. This makes it possible to enable or inhibit

CMOS AND Gate

CMOS OR Gate

time-varying analog signals having both positive and negative values. Conduction takes

place between the input and output terminals through MOSFETs Q1 and Q2. Positive current

(left to right in the diagram) flows through Q2, and negative current (right to left) flows

through Q1. Two inverters, consisting of the Q3/Q4 and Q5/Q6 pairs of MOSFETs, control

the ON/OFF state of the circuit.

When CONTROL _ 1, the inverters bias both Q1 and Q2 ON, allowing them to conduct.

When CONTROL _ 0, the circuit inhibits conduction between input and output.

The substrate terminal of Q1 is connected, not to the source terminal of that transistor,

but directly to VCC thus providing the correct bias to Q1 in the ON state.

A particular device with this function is the 74HC4066 quad analog switch, whose circuit

symbol is shown in Figure 11.59. When the CONTROL input is HIGH, analog and digital

signals can pass between the bidirectional input terminals.

FIGURE 11.58

CMOS Transmission Gate

One of Four Analog Switches From 74HC4066

❘❙❚ EXAMPLE 11.16 Figure 11.60 shows a circuit where the analog switches in a 74HC4066 package are used

to control the selection and muting of two pairs of speakers in a stereophonic audio system.

Briefly explain the circuit operation.

Solution The audio signal to each speaker is passed or blocked by a CMOS transmission

gate. The speakers are paired into A and B groups. Each pair has a left and a right

channel speaker. The same logic gate controls both speakers of each group.

The Select A switch enables the A speakers when it is open (logic HIGH). The Select

both sets of speakers when Q is LOW. This action inhibits both AND gates, making

all transmission gate CONTROL inputs LOW. The mute function toggles ON and OFF

with each push of the Mute ON/OFF switch.

❘❙❚

Standard (74NN) TTL and CMOS represented the two main standards of logic design for

many years, and their influence is still visible in other, more advanced types of logic. The

changes that have been made in newer logic families are not fundamental changes in the

working concepts, but improvements to the specifications, particularly switching speed

and power dissipation.

Example 11.16

74HC4066 Analog Switches as Audio Selectors

552 C H A P T E R 1 1 • Logic Gate Circuitry

TTL Logic Families

_0.4 V.

junction, which prevents the transistor from going into deep saturation.

transistors. Schottky TTL switches faster than standard TTL due to decreased storage

time in its transistors.

Speed-power product A measure of a logic circuit’s efficiency, calculated by

multiplying its propagation delay by its power dissipation. Unit: picojoule (pJ)

Probably the most important development in TTL technology was the introduction, in the

early 1970s, of the Schottky barrier diode into circuit designs. This made possible the first

family of nonsaturated bipolar logic, with its resultant improvement in switching speed.

Figure 11.61 shows a bipolar transistor with a Schottky diode connected across its

base and collector and the equivalent circuit symbol of this combination. We call this configuration

a Schottky transistor and logic devices using such transistors Schottky TTL.

K E Y T E R M S

FIGURE 11.61

Schottky Transistor

ON-State Operating Voltages of

Bipolar Transistors

Normally the base-collector junction of a saturated bipolar transistor has a drop of

about 0.5 volts, as shown in Figure 11.62. The Schottky diode clamps this junction voltage

to about 0.4 volts. This keeps the transistor out of deep saturation in its ON state. The base

region of the Schottky-clamped transistor holds less charge than does a standard bipolar

transistor. Its storage time, the time required to dissipate base charge upon turn-off, is substantially

reduced. The transistor can switch faster with the Schottky diode than without.

Figure 11.63 shows the circuits of the 74S00 Schottky and 74LS00 low-power Schottky

NAND gates. Compare these circuits to each other and to the 7400 standard TTL

NAND gate in Figure 11.33.

Schottky TTL Circuits

In the 74S00 circuit, Q1 acts as the input and Q2 as the phase splitter, as in the 7400

gate. The HIGH output circuit consists of Q3 and Q4 connected as a modified Darlington

pair. When Q2 is OFF (at least one input is LOW), enough base current flows in Q3 to turn

it on. Collector-emitter current in Q3 turns on Q4, making the output HIGH.

When Q2 is ON (both inputs are HIGH), the base of Q3 is pulled LOW, turning it OFF.

Sufficient current flows in the base of Q5 to turn it ON. The resultant current through Q5

will turn on Q6, making the output LOW. A similar analysis can be made for the 74LS00

gate.

One difference between the 74S00 and 74LS00 circuits is the size of the resistors; the

dissipation of the chip. The larger resistor values also slow down the switching times of the

various transistors by increasing the RC time constants of the circuit elements.

Speed-Power Product

One measure of logic circuit efficiency is its speed-power product, calculated by multiplying

switching speed and power dissipation, usually expressed in picojoules (pJ). (The

joule is the SI unit of energy. Power is the rate of energy used per unit time.) A major goal

of logic circuit design is the reduction of a device’s speed-power product.

Table 11.14 shows the propagation delay, supply current, and speed-power product for

a NAND gate in six TTL families: standard TTL (7400), Schottky (74S00), low-power

Schottky (74LS00), fast TTL (74F00), advanced Schottky (74AS00), and advanced lowpower

Schottky (74ALS00).

Table 11.14 TTL Speed and Power Specifications

7400 74LS00 74S00 74F00 74ALS00 74AS00

tpLH (max) 22 ns 15 ns 4.5 ns 6 ns 11 ns 4.5 ns

tpHL (max) 15 ns 15 ns 5 ns 5.3 ns 8 ns 4 ns

ICCH/4 (max) 2 mA 0.4 mA 4 mA 0.7 mA 0.21 mA 0.8 mA

ICCL/4 (max) 5.5 mA 1.1 mA 9 mA 2.6 mA 0.75 mA 4.35 mA

Speed-power product 605 pJ 82.5 pJ 225 pJ 78.0 pJ 41.25 pJ 97.9 pJ

(per gate)

The speed-power product shown is the worst-case value. This is calculated by multiplying

the largest value of ICC/4 by the slowest switching speed by 5 volts for each family.

We use ICC/4 because ICC is specified per chip (four gates).

A faster switching speed results in an overall increase in speed-power product, other

factors being equal. For example, the speed-power product of either advanced Schottky

family is lower than that of the LS and S families. However, the ALS series (the slower advanced

Schottky family) has a lower speed-power product than the AS series.

The smaller resistors used to speed up output switching imply a proportional drop in

propagation delay (higher speed) but an increased supply current. Power dissipation increases

in proportion to the square of the supply current, thus offsetting the effect of the increased

switching speed.

CMOS Logic Families

The CMOS gates we have looked at in this chapter are simpler than most gates actually in

use. There are two main families of CMOS devices: metal-gate CMOS, and silicon-gate, or

high-speed, CMOS.

There are two main variations on this type of circuit, designated B-series and UB-series

CMOS. Most CMOS gates are B-series; UB-series is available in a limited number of

inverting-type gates, such as inverters and 2-, 3-, and 4-input NAND and NOR gates. Figure

11.64 shows the difference in the two configurations.

Figure 11.64b shows one gate from a 4011UB quadruple 2-input NAND package. Its

circuit is the same as the NAND configuration examined in Section 11.8. Power supply

voltages in metal-gate CMOS are designated VDD (power) and VSS (ground). High-speed,

or silicon-gate, CMOS uses the same power supply designations as TTL: VCC and ground.

11.9 • TTL and CMOS Variations 555

The B-series configuration of this circuit has two additional inverter outputs in cascade

with theNANDlogic. (The same gate becomes anANDwhen we add a third output inverter.)

The inverter configuration is actually an amplifier; extra inverter stages provide additional

gain and increase noise margin by allowing the circuit to accept smaller input signals.

CMOS gates are sometimes used in analog applications, such as oscillators. The UBseries

gates, with their lower gain, are more desirable for such applications. Due to its low

switching speed, metal-gate CMOS is rarely used in new designs.

structure and thus higher speed than standard (metal-gate) CMOS.

Metal-gate CMOS has been considered a nearly ideal family for logic designs, with its high

noise immunity, low power consumption, and flexible power supply requirements. Unfortunately,

its propagation delay times, typically 10 to 20 times greater than those of equivalent

TTL devices, are just not fast enough for use in modern microprocessor-based systems.

striving to keep the other advantages of CMOS. This is achieved by using MOSFETs with

a polysilicon material for the gate, rather than metal, as in standard CMOS. Because of advantages

gained in this manufacturing process, each transistor is physically smaller and has

a lower gate capacitance than metal-gate MOSFETs. Both these factors contribute to a

lower propagation delay for the logic gate circuit.

Several subfamilies of high-speed CMOS are available for various logic and linear applications,

designated by the labels 74HCNN, 74HC4NNN, 74HCTNN, and 74HCUNN.

The 74HCNN series duplicates equivalent LSTTL functions in packages having identical

pinouts to LSTTL. The 74HC4NNN replaces CMOS functions pin for pin. Both these

series have CMOS-equivalent input and output levels, within the power supply limits (2.0

V to 6.0 V) of high-speed CMOS.

K E Y T E R M