Chapter 1 Basic Principles of Digital Systems outlin e 1
Discrete Separated into distinct segments or pieces. A series of discontinuous values. Dual slope ADC
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Discrete Separated into distinct segments or pieces. A series of discontinuous values. Dual slope ADC Also called an integrating ADC. An analogto- digital converter based on an integrator. The name derives from the fact that during the conversion process the integrator output changes linearly over time, with two different slopes. Flash converter (or simultaneous converter) An analog-todigital converter that uses comparators and a priority encoder to produce a digital code.
of a digital-to-analog converter. Integrator A circuit whose output is the accumulated sum of all previous input values. The integrator’s output changes linearly with time when the input voltage is constant.
a change in DAC reference voltage. Nyquist sampling theorem A theorem from information theory that states that, in order to preserve all information in a signal, it must be sampled at a rate of twice the highest-frequency component of the signal. (fs 2fmax) Priority encoder An encoder that will produce a binary output corresponding to the subscript of the highest-priority active input. This is usually defined as the input with the largest subscript. Quantization The number of bits used to represent an analog voltage as a digital number. Quantization error Inaccuracy introduced into a digital signal by the inability of a fixed number of bits to represent the exact value of an analog signal.
two adjacent digital codes. Analog step size. Sample An instantaneous measurement of an analog voltage, taken at regular intervals. Sample and hold circuit A circuit that samples an analog signal at periodic intervals and holds the sampled value long enough for an ADC to convert it to a digital code.
time of an analog signal. Successive approximation register A state machine used to generate a sequence of closer and closer binary approximations to an analog signal. P R O B L E M S Problem numbers set in color indicate more difficult problems: those with underlines indicate most difficult problems. Section 12.1 Analog and Digital Signals 12.1 An analog signal with a range of 0 to 12V is converted to a series of 3-bit digital codes. Make a table similar to Table 12.1 showing the analog range for each digital code.
of 12 V. Assume that this signal will be quantized according to the table constructed in Problem 12.1. Write the digital codes for the points 0, T/8, T/4, 3T/8, . . . , T where T is the period of the half sine wave.
in Problem 12.2. 12.5 An analog-to-digital converter divides the range of an analog signal into 64 equal parts. The analog input has a range of 0 to 500 mV. How many bits are there in the resultant digital codes? What is the resolution of the A/D converter?
256 equal parts. 12.7 The analog range of a signal is divided into m equal parts, yielding a digital quantization of n bits. If the range is divided into 2m parts, how many bits are in the equivalent digital codes? (That is, how many extra bits do we get for each doubling of the number of codes?)
DAC when the input code is 1010. b. Calculate Va for an 8-bit DAC when the input code is 10100000. c. Compare the results of parts a and b. What can you conclude from this comparison? 616 C H A P T E R 1 2 • Interfacing Analog and Digital Circuits 12.9 a. Calculate the analog output voltage, Va, for a 4-bit DAC when the input code is 1100. b. Calculate Va for an 8-bit DAC when the input code is 11001000. c. Compare the results of parts a and b. What can you conclude from this comparison? How does this differ from the comparison made in Problem 12.8?
For Iref _ 500 _A and RF _ 22 k_, calculate the range of analog output voltage, Va, if the DAC is a 4-bit circuit. Repeat the calculation for an 8-bit DAC. 12.11 The resistor for the MSB of a 16-bit weighted resistor D/A converter is 1 k_. List the resistor values for all bits. What component problem do we encounter when we try to build this circuit? 12.12 Draw the circuit for an 8-bit R-2R ladder DAC. 12.13 Calculate the value of Va of an R-2R ladder DAC when digital inputs are as follows. Vref _ 12 V. DCBA a. 1111 b. 1011 c. 0110 d. 0011 12.14 An MC1408 DAC is configured as shown in Figure 12.12. R14 _ R15 _ 6.8 k_, Vref(_) __12 V, Vref(_) _ ground, and RL _ 2.2 k_. Calculate the output voltage,
00000001, 10000000, 10101010, 11100010, 11111111. 12.15 Calculate the resolution of the DAC in Problem 12.14. 12.16 Refer to the op amp-buffered DAC in Figure 12.13. Assume the resistor values are changed as follows: R14A _ 270 _, R14B _ 2 k_ (max), RFA _ 1.2 k_, RFB _ 5 k_ (max). Describe a step-by-step procedure that calibrates the DAC so that it has a reference current of 4 mA and a full scale analog output voltage of 12 volts, using only a series of measurements of the analog output voltage. When the procedure is complete, what are the resistance values in the circuit? What is the range of the DAC?
12.13 allow us to set our input reference current and output gain to values within a specified range. Using the values shown in Figure 12.13, fill in Table 12.7 for the cases when Va is at minimum and maximum, and when the potentiometers are at their midpoint values. Assume the DAC input is set to 1111 1111. Show all calculations.
Minimum Va Maximum Va Pots at midpoint 12.18 The waveform in Figure 12.47 is observed at the output of the DAC ramp generator of Figure 12.14. (Compare this to the proper waveform, found in Figure 12.15.) What is likely to be the problem with the circuit? Can it be easily fixed? How?
of the DAC ramp generator in Figure 12.14. What is likely to be the problem with the circuit?
Problem 12.18 Waveform
Problem 12.19 Waveform Problems 617 12.20 Refer to the bipolar DAC circuit in Figure 12.16. Describe how you would adjust the output for a range of _10 V to (_10 V _ 2 LSB). Include values of variable components. Calculate the resolution of this circuit. 12.21 A 3-bit DAC has a reference voltage of 12 V and a transfer characteristic summarized in Table 12.8. Plot the data on a graph similar to those in Figures 12.18 through 12.20. From the data in Table 12.8, determine the offset error, gain error, and linearity error of the DAC, both in % of full scale and as a fraction of an LSB. 12.23 A 3-bit DAC has a reference voltage of 4 V and a transfer characteristic summarized in Table 12.10. Plot the data on a graph. From the data in the Table 12.10, determine the offset error, gain error, and linearity error of the DAC, both in % of full scale and as a fraction of an LSB.
for Problem 12.23 Digital Code Analog Output (volts) 000 0.000 001 0.500 010 1.025 011 1.525 100 1.985 101 2.675 110 3.000 111 3.500
flash converter? Sketch the circuit of this converter. (It is only necessary to show a few of the comparators and indicate how many there are.) 12.25 Briefly explain the operation of a flash ADC. What is the purpose of the priority encoder? Explain how the latch can be used to synchronize the output to a particular sampling frequency. 12.26 Why do we choose a value of R/2 for the LSB resistor of a flash ADC? 12.27 An 8-bit successive approximation ADC has a reference voltage of _16 V. Describe the conversion sequence for the case where the analog input is 4.75 V. Summarize the steps in Table 12.11. (Refer to Example 12.11.) 12.28 What is displayed on the seven-segment display in Figure 12.49 when vanalog _ 5.25 V? Assume that the reference voltage is 12 V and that the display can show hex digits.
ADC shown in Figure 12.49 when the analog input changes from 5.25 V to 8.0 V. What is the new number displayed on the seven-segment display? Table 12.8 DAC Transfer Characteristic for Problem 12.21 Digital Code Analog Output (volts) 000 0.5
001 2.0 010 3.5
011 5.0 100 6.5
101 8.0 110 9.5
111 11.0 12.22 A 3-bit DAC has a reference voltage of 8 V and a transfer characteristic summarized in Table 12.9. Plot the data on a graph. From the data in Table 12.9, determine the offset error, gain error, linearity error, and differential nonlinearity of the DAC, both in % of full scale and as a fraction of an LSB. Table 12.9 DAC Transfer Characteristic for Problem 12.22 Digital Code Analog Output (volts) 000 0.000 001 1.036 010 2.071 011 3.107 100 4.143 101 5.179 110 6.214 111 7.250
voltage of 12 V. Calculate the resolution of this ADC.
Can this input voltage be represented exactly? What digital code represents the closest value to 8 V? What exact analog value does this represent? Calculate the percent error of this conversion.
to a fraction of 1 LSB? 12.32 An 8-bit dual slope analog-to-digital converter has a reference voltage of 16 V. The integrator component values are: R _ 80 k_, C _ 0.1 _F. The analog input voltage is 14 V.
Calculate the slope of the integrator voltage during: a. the integrating phase, and b. the rezeroing phase. c. How much time elapses during the rezeroing phase? (Assume that (1) the integrating and rezeroing time are equal if the integrator output is at full scale, and (2) the reference voltage will rezero the integrator from full scale in exactly one counter cycle.)
the conversion is complete? 12.33 Repeat Problem 12.32 if the analog input voltage is 3 V. 12.34 Repeat Problem 12.32 if the analog input voltage is 18 V. 12.35 make a sketch of a basic sample and hold circuit and briefly explain its operation. 12.36 Explain why a sample and hold circuit may be needed at the input of an analog-to-digital converter. 12.37 What is the highest-frequency component of an analog signal that can be accurately represented digitally if it is sampled at a rate of 100 kHz?
preserve all information when sampling a sine wave with a frequency of 130 kHz.
every 5.2 _s. What alias frequency will result? (Hint: see Figure 12.33.)
anADC with a sampling frequency of 8 kHz. What type of filter (low-pass, high-pass, bandpass, etc.) is required?
Write a VHDL file to implement the continuous-convert version of the ADC controller, as represented in the state diagram of Figure 12.42. Create a simulation in MAX_PLUS II to verify the operation of the controller.
octal latch as components in aVHDL hierarchy that represents the ADC interface of Figure 12.38. Create a simulation inMAX_PLUSII to verify the operation of the design. 12.43 The data acquisition system in Figure 12.38 is designed with the controller from Problem 12.41. (The controller state diagram is shown in Figure 12.42.) Assume the controller and latch are interfaced with a different ADC that has a conversion time of 16 _s, which is equivalent to 64 clock cycles. Calculate the highest-frequency component that can be accurately converted with this system for a clock rate of 787 kHz. 12.44 Repeat Problem 12.43 for a 4-channel data acquisition system, assuming the same conversion rate for the ADC and the controller state diagram of Figure 12.45.
Problem 12.28 Successive Approximation Display Answers 619 A N S W E R S T O S E C T I O N R E V I E W P R O B L E M S Section 12.1 12.1 5 bits (25 _ 32). Resolution _ 24 mV/32 steps _ 0.75 mV/step.
Section 12.2a 12.2 4-bit: Ia _ 0 to (15/16)(1 mA) _ 0 to 0.9375 mA; Va _ _IaRF _ 0 to _9.375 V 8-bit: Ia _ 0 to (255/256)(1 mA) _ 0 to 0.9961 mA; Va _ 0 to _9.961 V
lower range of output voltage. Section 12.2e 12.6 The output 0 V requires its own code. This leaves 255, not 256, codes for the remaining output values. The maximum value of a positive-only output is 255/256 of the reference voltage. A bipolar DAC ranges from _128/128 to _127/128 of the reference voltage.
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Memory Devices and Systems O U T L I N E
Concepts
13.2 Random Access Read/Write Memory (RAM)
(ROM)
13.4 Sequential Memory: FIFO and LIFO 13.5 Dynamic RAM Modules
13.6 Memory Systems C H A P T E R O B J E C T I V E S Upon successful completion of this chapter, you will be able to: • Describe basic memory concepts of address and data. • Understand how latches and flip-flops act as simple memory devices and sketch simple memory systems based on these devices. • Distinguish between random access read/write memory (RAM) and read only memory (ROM). • Describe the uses of tristate logic in data bussing. • Sketch the circuits of static and dynamic RAM cells. • Sketch a block diagram of a static or dynamic RAM chip. • Describe various types of ROM cells and arrays: mask-programmed, UV erasable, and electrically erasable. • Use various types of ROM in simple applications, such as digital function generation. • Describe the basic configuration of flash memory. • Describe the basic configuration and operation of two types of sequential memory: first-in-first-out (FIFO) and last-in-first-out (LIFO). • Describe how dynamic RAM is configured into high capacity memory modules.
• Sketch a basic memory system, consisting of several memory devices, an address and a data bus, and address decoding circuitry. • Represent the location of various memory device addresses on a system memory map. • Recognize and eliminate conditions leading to bus contention in a memory system.
• Expand memory capacity by parallel bussing and CPLD-based decoding. 622 C H A P T E R 1 3 • Memory Devices and Systems In recent years, memory has become one of the most important topics in digital electronics. This is tied closely to the increasing prominence of cheap and readily available microprocessor chips. The simplest memory is a device we are already familiar with: the D flip-flop. This device stores a single bit of information as long as necessary. This simple concept is at the heart of all memory devices. The other basic concept of memory is the organization of stored data. Bits are stored in locations specified by an “address,” a unique number which tells a digital system how to find data that have been previously stored. (By analogy, think of your street address: a unique way to find you and anyone you live with.) Some memory can be written to and read from in random order; this is called random access read/write memory (RAM). Other memory can be read only: read only memory (ROM). Yet another type of memory, sequential memory, can be read or written only in a specific sequence. There are several variations on all these basic classes. Memory devices are usually part of a larger system, including a microprocessor, peripheral devices, and a system of tristate busses. If dynamic RAM is used in such a system, it is often in a memory module of some type. The capacity of a single memory chip is usually less than the memory capacity of the microprocessor system in which it is used. In order to use the full system capacity, it is necessary to use a method of memory address decoding to select a particular RAM device for a specified portion of system memory. 13.1 Basic Memory Concepts
for later use in a digital system. Data Binary digits (0s and 1s) that contain some kind of information. The digital contents of a memory device. Address A number, represented by the binary states of a group of inputs or outputs, uniquely defining the location of data stored in a memory device. Write Store data in a memory device. Read Retrieve data from a memory device. Byte A group of 8 bits. Nibble Half a byte; 4 bits. Address and Data A memory is a digital device or circuit that can store one or more bits of data. The simplest memory device, a D-type latch, shown in Figure 13.1, can store 1 bit. A 0 or 1 is stored in the latch and remains there until changed. A simple extension of the single D-type latch is an array of latches, shown in Figure 13.2, that can store 8 bits (1 byte) of data. Figure 13.3 shows this octal latch used as a component in a MAX_PLUS II graphic file and configured as an 8-bit memory. When the WRITEn line goes LOW, then HIGH, data at the DATA_IN are stored in the eight latches. Data are available at the DATA_OUT pins when READ is HIGH. Note that although the READ and WRITEn inputs are separate in this design, their functions would often be implemented as opposite logic levels of the same pin. Figure 13.4 shows a simulation of the 8-bit memory. The LOW pulses on WRITEn write the data, shown as two hexadecimal digits on the DATA_IN line, into the latches. To read the values stored in the eight latches, we set READ HIGH. In between read states, all
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