Chapter 1 Basic Principles of Digital Systems outlin e 1

accuracy. It measures the deviation of the actual from the ideal output voltage as a

fraction of the full-scale voltage. The MC1408 DAC has a relative accuracy of __1

2

_ LSB _

2

_ LSB

ns for 8-bit accuracy, limiting its output switching frequency to 1/300 ns _ 3.33 MHz. Depending

on the value of R4, the output resistor, the settling time of the MC1408 may increase

to as much as 1.2 _s when the Range input is open.

gain of a DAC is too high, the output saturates before reaching the maximum output code.

Figure 12.18 shows the effect of gain error in a 3-bit DAC. In the high gain response, the

last two input codes (110 and 111) produce the same output voltage.

DAC Monotonicity

0

1/8 FS

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

code

1/4 FS

1/2 FS

3/4 FS

FS

Analog output

approximation

0

1/8 FS

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

code

1/4 FS

1/2 FS

3/4 FS

FS

Analog output

for increasing input

increase with increasing digital input codes. Figure 12.19 shows this error. A linearity

error of more than __1

2

_ LSB can result in a nonmonotonic output. For example, in Figure

it results in a change of __1

2

_ LSB. This is an error of _1_1

_ LSB, resulting in a nonmonotonic

output.

In Figure 12.19, the code for 011 has a linearity error of __1

_ LSB and the adjacent code

(100) has a linearity error of __1

2

_ LSB, yielding a flat output for the two codes. This makes

0

1/8 FS

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

code

3/8 FS

5/8 FS

7/8 FS

Analog output

Gain too high

"Normal" gain

Saturated output

for high codes

Gain too low

(max. code does

not reach (FS _ 1 LSB))

FIGURE 12.18

DAC Gain Errors

0

1/8 FS

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

code

3/8 FS

5/8 FS

7/8 FS

Analog output

Nonlinear

response

response

_ 1/2 LSB

DAC Linearity Error

expected step size of a DAC when the input code is changed by 1 LSB. An actual step that

is smaller than the expected step can result in a nonmonotonic output.

Offset error. This error occurs when the analog output of a positive-value DAC is not

0 V when the input code is all 0s. Figure 12.20 shows the effect of offset error.

❘❙❚ EXAMPLE 12.9 An 8-bit DAC has an output range of 0 to (_8 volts _ 1 LSB). The hexadecimal value of

the input is symbolized by x.

a. What is the value of 1 LSB?

b. Assuming an ideal DAC, what would the output be for a binary input x _ C0H?

c. If the DAC has an input of x _ 00H and the output voltage is 0.008 V, calculate the offset

error (OE) of the DAC in LSB and as a percentage of the full scale (FS). Assume no

other errors.

d. If the DAC has an input of x _ FFH and the output voltage is 7.98 V, calculate the gain

error (GE) of the DAC in LSB and as a percentage of the full scale (FS). Assume no

other errors.

e. If the DAC output is 4 V for an input x _ 80H and the output is 0.015 V for an input of

x _ 00H, calculate the linearity error (LE) and offset error (OE) of the DAC in LSB and

as a percentage of the full scale (FS).

a. 1 LSB _ FS/2n _ 8 V/28 _ 8 V/256 _ 31.25 mV

b. C0H _ 19210

Va _ (code/256) 8 V _ (192/256) 8 V _ 6 V

alternatively: C0H _ 11000000, which corresponds to _3

4

_ FS _ 6 V

0

1/8 FS

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

code

3/8 FS

5/8 FS

7/8 FS

Analog output

Ideal response

Offset

Response with

offset error

FIGURE 12.20

DAC Offset Error

d. When x _ FFH, Va should be (255/256) 8 V _ 7.969 V. GE _ 7.98 V _ 7.96875 V _

11.25 mV.

GE[LSB] _ 11.25 mV/31.25 mV _ 0.36 LSB

GE[%FS] _ (11.25 mV/8 V) _ 100% FS _ 0.14% FS

e. Without accounting for other possible errors, the output value for an input of 80H appears

to be correct. However, we find an offset error of 0.015 V that must be subtracted

out of all measured values in the DAC output.

Adjusted value at 80H _ 4 V _ 0.015 V _ 3.985 V. This error is exactly balanced by

the offset error, so both have the same value.

❘❙❚

We saw in an earlier section of this chapter that all digital-to-analog converters can be described

by a generic form. This is not true of analog-to-digital converters. There are many

circuits for converting analog signals to digital codes, each with its own advantages. We

will look at several of the most popular.

Flash A/D Converter

uses comparators and a priority encoder to produce a digital code.

the subscript of the highest-priority active input. This is usually defined as the input

with the largest subscript.

Figure 12.21 shows the circuit for a 3-bit flash analog-to-digital converter. The circuit

consists of a resistive voltage divider, seven analog comparators, a priority encoder, and

an output latch array.

The voltage divider has a total resistance of 8R. The resistors are selected to produce

seven equally spaced reference voltages (Vref/16, 3Vref/16, 5Vref/16, . . . 15Vref/16; each is

separated by Vref/8). Each reference voltage is fed to the inverting input of a comparator.

A comparator output goes HIGH if the voltage at its noninverting (_) input is higher

than the voltage at its inverting (_) input. If the (_) input voltage is greater than the (_)

input voltage, the comparator output is LOW.

The analog voltage, Va, is applied to the noninverting inputs of all comparators simultaneously.

Thus, if the analog voltage exceeds the reference voltage of a particular comparator,

that comparator switches its output to the HIGH state.

For most analog input values, more than one comparator will have a HIGH output. For

example, the reference voltage of comparator 3 is (5Vref/16). Comparator 4 has a reference

voltage of (7Vref/16). If the analog voltage is in the range (5Vref/16) _ Va _ (7Vref/16),

comparators 3, 2, and 1 all have HIGH outputs and comparators 4, 5, 6, and 7 all have

LOW outputs.

The priority encoder recognizes that input D3 is the highest-priority active input and

produces the digital code 011 at its outputs. The output latches store this value when the

K E Y T E R M S

We can regularly sample an analog signal by applying a pulse waveform to the CLK

input of the latch circuit. The sampling frequency is the same as the clock frequency.

The D0 input of the priority encoder is grounded, rather than connected to a comparator

output. No comparator is needed for this input; if Va _ (Vref/16), all comparator outputs

are LOW and the resulting digital code is 000.

Figure 12.22 shows the transfer characteristic of the flash ADC with a reference voltage

of 8 V. The digital steps are centered on the analog voltages that are whole-number fractions

(1/8, 1/4, 3/8, . . . 7/8) of the reference voltage. The transitions are midway between these

points. This is why the resistor for the least significant bit is R/2, rather than R.

Flash Converter (ADC)

Transfer Characteristic of Flash

ADC

12.3 • Analog-to-Digital Conversion 593

The general form of this circuit has 2n _ 1 comparators for an n-bit output. For example,

an 8-bit flash converter has 28 _ 1 _ 255 comparators. For any large number of bits,

the circuit becomes overly complex.

The main advantage of this circuit is its speed. Since the analog input is compared to the

threshold values of all possible input codes at one time, conversion occurs in one clock cycle.

Successive Approximation A/D Converter

Successive approximation register A state machine used to generate a sequence

of closer and closer binary approximations to an analog signal.

a fixed number of bits to represent the exact value of an analog signal.

Probably the most widely used type of analog-to-digital converter is the successive approximation

ADC. The idea behind this type of converter is a technique a computer programmer

would call “binary search.”

The analog voltage to be converted is a number within a defined range. The search

technique works by narrowing down progressively smaller binary fractions of the known

range of numbers.

Suppose we know that the analog voltage is a number between 0 and 255, inclusive.

We can find the binary value of any randomly chosen number in this range in no more than

eight guesses, or approximations, since 28 _ 256. Each approximation adds one more bit

to the estimated digital value.

The first approximation determines which half of the range the number is in. The second

test finds which quarter of the range, the third test which eighth, the fourth test which

sixteenth, and so on until we run out of bits.

❘❙❚ EXAMPLE 12.10 Use a binary search technique to find the value of a number in the range 0 to 255. (The

number is 44.)

Solution

1. The number must be in the upper or lower half of the range. Cut the range in half:

0–127, 128–125.

Is x 128? No. 0 _ x _ 128.

2. Cut the remaining range in half: 0–63, 64–127.

Is x 64? No. 0 _ x _ 64.

3. Cut the remaining range in half: 0–31, 32–63.

Is x 32? Yes. 32 _ x _ 64.

4. Cut the remaining range in half: 32–47, 48–63.

Is x 48? No. 32 _ x _ 48.

5. Cut the remaining range in half: 32–39, 40–47.

Is x 40? Yes. 40 _ x _ 48.

6. Cut the remaining range in half: 40–43, 44–47.

Is x 44? Yes. 44 _ x _ 48.

7. Cut the remaining range in half: 44–45, 46–47.

Is x 46? No. 44 _ x _ 46.

8. Cut the remaining range in half: 44–45.

Is x 45? No. x _ 44.

❘❙❚

K E Y T E R M S

The test criteria for each step in Example 12.10 are phrased so that the answer is always

yes or no. (For example, x 64? can only be answered yes or no.) Assume that a 1

means yes and a 0 means no. The tests in Example 12.10 give the following sequence of results:

00101100. The decimal equivalent of this binary number is 44, our original value.

A successive approximation ADC such as the one shown in Figure 12.23 applies a

similar technique. The circuit has three main components: an analog comparator, a digitalto-

analog converter, and a state machine called a successive approximation register

(SAR). The SAR is an 8-bit register whose bits can be set and cleared individually,

according to a specific control sequence and the logic value at the output of the analog

comparator.

When a pulse activates the Start Conversion input, bit Q7 of the SAR is set. This

makes the SAR output 10000000. The DAC converts the SAR output to an analog equivalent.

When only the MSB is set, this is one half the reference voltage of the DAC.

The DAC output voltage is compared to an analog input voltage. (In effect, the SAR

asks, “Is this approximation greater or less than the actual analog voltage?”)

If Vanalog VDAC, the comparator output is HIGH and the MSB remains set. Otherwise,

the comparator output is LOW and the MSB is cleared. The process is repeated for

all bits.

After all bits have been set or cleared, the End of Conversion (EOC) output changes

state. This can be used to load the final digital value into an 8-bit latch.

❘❙❚ EXAMPLE 12.11

An 8-bit successive approximation ADC has an analog input voltage of 9.5 V. Describe the

steps the circuit performs to generate an 8-bit digital equivalent value if the DAC in the circuit

has a reference voltage of 12 V.

Solution Figure 12.24 shows the steps the converter performs to generate the 8-bit digital

equivalent of 9.5 V. The conversion process is also summarized in Table 12.4.

Successive Approximation ADC

Example 12.11

Successive Approximation A/D Conversion

Table 12.4 8-Bit Successive Approximation Conversion

Accumulated Digital

Bit New Digital Value Analog Equivalent Vanalog VDAC? Comparator Output Value

Q7 10000000 6 V Yes 1 10000000

Q6 11000000 9 V Yes 1 11000000

Q5 11100000 10.5 V No 0 11000000

Q4 11010000 9.75 V No 0 11000000

Q3 11001000 9.375 V Yes 1 11001000

Q2 11001100 9.5625 V No 0 11001000

Q1 11001010 9.46875 V Yes 1 11001010

Q0 11001011 9.515625 V No 0 11001010

596 C H A P T E R 1 2 • Interfacing Analog and Digital Circuits

The following steps occur for each bit:

1. The bit is set.

2. The digital output is converted to an analog voltage and compared to the actual analog

input.

3. If the analog voltage is greater than the DAC output voltage, the bit remains set. Otherwise

❘❙❚

(9.5 V). The final answer is within 13 mV, out of 12 V, which is pretty close but not exact.

This difference is called quantization error. The maximum value of quantization error is

__1

_ LSB for any ADC, except on the lowest step, where the error is __1

2

_, _0 LSB, and on

2

_ LSB.

approximation acquires more decimal places of accuracy. Note that once the analog value

extends beyond the decimal point, the last decimal digit is always 5.

An advantage of a successive approximation ADC is that the conversion time is always

the same, regardless of the analog input voltage. This is not true with all types of analog-

to-digital converters. The constant conversion time allows the output to be synchronized

so that it can be read at known intervals.

The conversion time can be as few as (n _ 1) clock pulses for an n-bit device, if a bit

is set by a clock edge and cleared asynchronously or by the opposite clock edge. Some

SARs require four or more clock pulses per bit.

Dual Slope A/D Converter

Integrator A circuit whose output is the accumulated sum of all previous input

values. The integrator’s output changes linearly with time when the input voltage is

constant.

Dual slope ADC Also called an integrating ADC. An analog-to-digital converter

based on an integrator. The name derives from the fact that during the conversion

process the integrator output changes linearly over time, with two different slopes.

A dual slope analog-to-digital converter is based on an integrator circuit, such as the

one shown in Figure 12.25. The circuit output is proportional to the integral of the input

K E Y T E R M S

Integrator

voltage as a function of time. Integration with respect to time is the summing of instantaneous

values of a function over a specified period of time. In other words, the output of an

integrator is the accumulated total of all previous values of input voltage.

We can analyze the circuit without calculus under special conditions, such as when the

input voltage is constant. An integrator is similar to an inverting amplifier and can be analyzed

using similar techniques. Since the input impedance of the op amp is large, there is

very little current flowing into its (_) terminal. Ohm’s law thus implies that there is very

little voltage difference between the (_) and (_) terminals. Since they are at almost the

same potential and the (_) terminal is grounded, we can say that the (_) terminal is “virtually

grounded.”

If the input voltage is constant, a DC current, I, flows in R. Since R is connected to the

positive terminal of the input voltage source at one end and virtual ground at the other, the

entire source voltage drops across the resistor. By Ohm’s law,

Since the op amp input impedance is large, most current flows into the capacitor,

causing it to charge over time. The current direction defines a polarity for Vc, the capacitor

voltage.

connected from the op amp output to virtual ground. Therefore, the output voltage,

opposite:

The capacitor voltage is determined by the stored charge, Q, and the value of capacitance,

The current I is the amount of charge flowing past a given point in a fixed time:

Thus,

and

Substitute the expression for I into this equation to get

The output of an integrator with a constant input changes linearly with time, with a slope

equal to __

R

V

C

in _.

This equation describes the change in output voltage due to a constant input. When the

input goes to 0 V, the capacitor holds its charge (ideally forever; in practice until it leaks

away through circuit impedances) and maintains the output voltage at its final value. If a

new input voltage is applied, we can use the integrator equation to calculate the change in

output, which must then be added to the previous value.

❘❙❚ EXAMPLE 12.12 The integrator circuit of Figure 12.25 has the following component values:

C _ 0.025 _F, R _ 10 k_

Sketch the graph of the output voltage if the waveform shown in the graph of Figure

12.26a is applied to the integrator input. The integrator output is originally at 0 V.