FIGURE 12.1 Analog Input and Output Signals Table 12.1

Analog Input and Output Signals

for 0 to 8 V Analog Range

0.00–0.25 0000

0.25–0.75 0001

0.75–1.25 0010

1.25–1.75 0011

1.75–2.25 0100

2.25–2.75 0101

2.75–3.25 0110

3.25–3.75 0111

3.75–4.25 1000

4.25–4.75 1001

4.75–5.25 1010

5.25–5.75 1011

5.75–6.25 1100

6.25–6.75 1101

6.75–7.25 1110

7.25–8.00 1111

12.1 • Analog and Digital Signals 569

The analog input is sampled and converted at the beginning of each time division on

the graph. The 4-bit digital code does not change until the next conversion, 1 ms later.

This is the same as saying that the system has a sampling frequency of 1 kHz ( f _ 1/T _

1/(1 ms) _ 1 kHz).

Table 12.2 shows the digital codes for samples taken from t _ 0 to t _ 18 ms. The analog

voltages in Table 12.2 are calculated by the formula

Vanalog _ 8 V sin (t _ (10°/ms))

For example at t _ 2 ms, Vanalog _ 8 V sin (2 ms _ (10°/ms)) _ 8 V sin (20°) _ 2.736 V.

The calculated analog values are compared to the voltage ranges in Table 12.1 and assigned

the appropriate code. The value 2.736 V is between 2.25 V and 2.75 V and therefore

is assigned the 4-bit value of 0101.

Table 12.2 4-bit Codes for a Sampled Analog Signal

Time (ms) Analog Amplitude (volts) Digital Code

0 0.000 0000

1 1.389 0011

2 2.736 0101

3 4.000 1000

4 5.142 1010

5 6.128 1100

6 6.928 1110

7 7.518 1111

8 7.878 1111

9 8.000 1111

10 7.878 1111

11 7.518 1111

12 6.928 1110

13 6.128 1100

14 5.142 1010

15 4.000 1000

16 2.736 0101

17 1.389 0011

18 0.000 0000

0 0.000 00000000

1 1.389 00101100

2 2.736 01011100

3 4.000 10000000

4 5.142 10100101

5 6.128 11000010

6 6.928 11011110

7 7.518 11110001

8 7.878 11111100

9 8.000 11111111

10 7.878 11111100

11 7.518 11110001

12 6.928 11011110

13 6.128 11000010

14 5.142 10100101

15 4.000 10000000

16 2.736 01011100

17 1.389 00101100

18 0.000 00000000

The digital-to-analog converter in Figure 12.1 continuously converts the digital codes

to their analog equivalents. Each code produces an analog voltage whose value is the midpoint

of the range corresponding to that code.

For this particular analog waveform, the A/D converter introduces the greatest inaccuracy

at the peak of the waveform, where the magnitude of the input voltage changes the

least per unit time. There is not sufficient difference between the values of successive analog

samples to map them into unique codes. As a result, the output waveform flattens out at

the top.

analog ranges in the signal. By using more bits, we could divide the analog signal

into a greater number of smaller ranges, allowing more accurate conversion of a signal

having small changes in amplitude. For example, an 8-bit code would give us 256 steps

(a resolution of 8 V/256 _ 31.25 mV). This would yield the code assignments shown

in Table 12.3. Note that for an 8-bit code, there is a unique value for every sampled

voltage.

Figure 12.2 shows how different levels of quantization affect the accuracy of a digital

representation of an analog signal. The analog input is a sine wave, converted to digital

570 C H A P T E R 1 2 • Interfacing Analog and Digital Circuits

codes and back to analog, as in Figure 12.1. The graphs show the analog input and three

analog outputs, each of which has been sampled 28 times per cycle, but with different

quantizations. The corresponding digital codes range from a maximum negative value of n

0s to a maximum positive value of n 1s for an n-bit quantization (e.g., for a 4-bit quantization,

maximum negative _ 0000, maximum positive _ 1111).

The first output signal has an infinite number of bits in its quantization. Even the

smallest analog change between samples has a unique code. This ideal case is not attainable,

since a digital circuit always has a finite number of bits. We can see from the codes in

Table 12.3 that an 8-bit quantization is sufficient to give unique codes for this waveform.

An infinite quantization implies that the resolution is small enough that each sampled voltage

can be represented, not only by a unique code, but as its exact value rather than a point

within a range.

The 4-bit and 3-bit quantizations in the next two graphs show progressively worse representation

of the original signal, especially at the peaks. The change in analog voltage is

too small for each sample to have a unique code at these low quantizations.

Figure 12.3 shows how the digital representation of a signal can be improved by

increasing its sampling frequency. It shows an analog signal and three analog waveforms

resulting from an analog-digital-analog conversion. All waveforms have infinite

quantization, but different numbers of samples in the analog-to-digital conversion. As

the number of samples decreases, the output waveform becomes a poorer copy of the

input.

waveform and the quantization affects the vertical resolution.

Effect of Quantization

❘❙❚ SECTION 12.1 REVIEW PROBLEM

12.1 An analog signal has a range of 0 to 24 mV. The range is divided into 32 equal steps

for conversion to a series of digital codes. How many bits are in the resultant digital

codes? What is the resolution of the A/D converter?

12.2 Digital-to-Analog Conversion

Full scale The maximum analog reference voltage or current of a digital-toanalog

converter.

Figure 12.4 shows the block diagram of a generalized digital-to-analog converter. Each

digital input switches a proportionally weighted current on or off, with the current for the

MSB being the largest. The second MSB produces a current half as large. The current generated

by the third MSB is one quarter of the MSB current, and so on.

These currents all sum at the operational amplifier’s (op amp’s) inverting input. The

total analog current for an n-bit circuit is given by:

The bit values b0, b1, . . . bn can be only 0 or 1. The function of each bit is to include

or exclude a term from the general expression.

K E Y T E R M

Effect of Sampling Frequency

The op amp acts as a current-to-voltage converter. The analysis, illustrated in Figure

12.4b, is the same as for an inverting op amp circuit with a constant input current.

The input impedance of the op amp is the impedance between its inverting (_) and

noninverting (_) terminals. This value is very large, on the order of 2 M_. If this is large

compared to other circuit resistances, we can neglect the op amp input current, Iin.

This implies that the voltage drop across the input terminals is very small; the inverting

and noninverting terminals are at approximately the same voltage. Since the noninverting

input is grounded, we can say that the inverting input is “virtually grounded.”

Current IF flows in the feedback loop, through resistor RF. Since Ia _ Iin _ IF _ 0 and

resistor is connected to the output at one end and to virtual ground at the other. The op

amp output voltage is measured with respect to ground. The two voltages are effectively in

parallel. Thus, the output voltage is the same as the voltage across the feedback resistor,

with a polarity opposite to VF, calculated above.

Va _ _VF _ _Ia RF

_ Iref RF

The range of analog output voltage is set by choosing the appropriate value of RF.

❘❙❚ EXAMPLE 12.1 Write the expression for analog current, Ia, of a 4-bit D/A converter. Calculate values of Ia

for input codes b3b2b1b0 _ 0000, 0001, 1000, 1010, and 1111, if Iref _ 1 mA.

Solution The analog current of a 4-bit converter is:

Ia _

b3 23 _ b2 22 _ b1 21 _ b0 20

24 Iref

_bn_12n_1 _ _ _ _ _ b2 22 _ b1 21 _ b0 20

_____

Analysis of a Generalized

Digital-to-Analog Converter

12.2 • Digital-to-Analog Conversion 573

_

8b3 _ 4b2 _ 2b1 _ b0 (1 mA)

(0 _ 0 _ 0 _ 0)(1 mA)

_ 0

16

b3b2b1b0 _ 0001, Ia _

_

1 mA

16 16

(8 _ 0 _ 0 _ 0)(1 mA)

_

8

(1 mA) _ 0.5 mA

(8 _ 0 _ 2 _ 0)(1 mA)

_

10

(1 mA) _ 0.625 mA

(8 _ 4 _ 2 _ 1)(1 mA)

_

15

(1 mA) _ 0.9375 mA

❘❙❚

the reference current Iref. The denominator of the fraction is 2n for an n-bit converter. The

numerator is the decimal equivalent of the binary input. For example, for input b3b2b1b0 _

0111, Ia _ (7/16)(Iref).

Note that when b3b2b1b0 _ 1111, the analog current is not the full value of Iref, but

15/16 of it. This is one least significant bit less than full scale.

This is true for any D/A converter, regardless of the number of bits. The maximum

analog current for a 5-bit converter is 31/32 of full scale. In an 8-bit converter, Ia cannot exceed

255/256 of full scale. This is because the analog value 0 has its own code. An n-bit

converter has 2n input codes, ranging from 0 to 2n _ 1.

The difference between the full scale (FS) of a digital-to-analog converter and its maximum

output is the resolution of the converter. Since the resolution is the smallest change in

output, equivalent to a change in the least significant bit,wecan define themaximumoutput as

FS_1 LSB. (As an example, in the case of an 8-bit converter FS_1LSB_255/256 Iref.)

❘❙❚ SECTION 12.2A REVIEW PROBLEM

12.2 Calculate the range of analog voltage of a 4-bit D/A converter having values of

Weighted Resistor D/A Converter

Figure 12.5 shows the circuit of a 4-bit weighted resistor D/A converter. The heart of this

circuit is a parallel network of binary-weighted resistors. The MSB has a resistor value of

branch currents decrease by halves with each descending bit value.

Weighted Resistor D-to-A

Converter

574 C H A P T E R 1 2 • Interfacing Analog and Digital Circuits

The bit inputs, b3, b2, b1, and b0, are either 0 V or Vref. When the corresponding bits are

HIGH, the branch currents are:

I3 _ Vref/R

I2 _ Vref/2R

I1 _ Vref/4R

I0 _ Vref/8R

The sum of branch currents gives us the analog current Ia.

We can calculate the analog voltage by Ohm’s law:

V2 _ _Ia RF _ _Ia (R/2)

_ _ __

1

3_

2

2_

4

1_

8

0_

ref _ _

2

_

1

3_

2

2_

4

1_

8

0_

2

ref _

2

3_

4

2_

8

1_

1

b

6

0_

_ Vref

❘❙❚ EXAMPLE 12.2 Calculate the analog voltage of a weighted resistor D/A converter when the binary inputs

have the following values: b3b2b1b0 _ 0000, 1000, 1111. Vref _ 5 V.

Solution

b3b2b1b0 _ 0000

Va _ _ __

0

2

0

4

0

8

1

0

__ Vref _ 0

1

2

0

4

0

8

1

0

__ Vref _ __

1

2

_ (5 V) _ _2.5 V

1

2

1

4

1

8

1

1

__ Vref _ __

1

1

5

_ (5 V) _ _4.69 V

❘❙❚

The weighted resistor DAC is seldom used in practice. One reason is the wide range of

resistors whose values are sufficiently precise.

A 4-bit converter needs a range of resistors from R to 8R. If R _ 1 k_, then 8R _ 8

k_. An 8-bit DAC must have a range from 1 k_ to 128 k_. Standard value resistors are

specified to two significant figures; there is no standard 128-k_ resistor. We would need to

use relatively expensive precision resistors for any value having more than two significant

figures.

I

b V

R

b V

R

b V

R

b V

R

b b b b V

R

a







3 2 1 0

1 2 4 8

ref

Another DAC circuit, the R-2R ladder, is more commonly used. It requires only two

values of resistance for any number of bits.

❘❙❚ SECTION 12.2B REVIEW PROBLEM

12.3 The resistor for the MSB of a 12-bit weighted resistor D/A converter is 1 k_. What is

the resistor value for the LSB?

R-2R Ladder D/A Converter

Figure 12.6 shows the circuit of an R-2R ladder D/A converter. Like the weighted resistor

DAC, this circuit produces an analog current that is the sum of binary-weighted currents.

An operational amplifier converts the current to a proportional voltage.

R-2R Ladder DAC

The circuit requires an operational amplifier with a high slew rate. Slew rate is the rate

at which the output changes after a step change at the input. If a standard op amp (e.g.,

741C) is used, the circuit will not accurately reproduce changes introduced by large

changes in the digital input.

The method of generating the analog current for an R-2R ladder DAC is a little

less obvious than for the weighted resistor DAC. As the name implies, the resistor network

is a ladder that has two values of resistance, one of which is twice the other. This

circuit is expandable to any number of bits simply by adding one resistor of each value

for each bit.

The analog output is a function of the digital input and the value of the op amp feedback

resistor. If logic HIGH _ Vref, logic LOW _ 0 V, and RF _ R, the analog output is

given by:

2

3_

4

2_

8

1_

1

b

6

0_

_ Vref

circuit and treat the circuit as an inverting amplifier. Figure 12.7 shows the equivalent

circuit for the input code b3b2b1b0 _ 1000.

Figure 12.8a shows the equivalent circuit of the R-2R ladder when b3b2b1b0 _ 1000.

All LOW bits are grounded, and the HIGH bit connects to Vref. We can reduce the network

to two resistors by using series and parallel combinations.

The two resistors at the far left of the ladder are in parallel: 2R _ 2R _ R. This equivalent

resistance is in series with another: R _ R _ 2R. The new resistance is in parallel with

yet another: 2R _ 2R _ R. We continue this process until we get the simplified circuit

shown in Figure 12.8b.

Next, we find the Thévenin equivalent of the simplified circuit. To find ETh, calculate

the terminal voltage of the circuit, using voltage division.

ETh _ _

2R

2

_

R

source short-circuited. Its value is that of the two resistors in parallel: RTh _ 2R _ 2R _ R.

Equivalent Circuit for

R-2R Circuit Analysis for

The value of the Thévenin resistance of the R-2R ladder will always be R, regardless

of the digital input code. This is because we short-circuit any voltage sources

when we make this calculation, which grounds the corresponding bit resistors. The

other resistors are already grounded by logic LOWs. We reduce the circuit to a single

resistor, R, by parallel and series combinations of R and 2R. Figure 12.9 shows

the equivalent circuit.

FIGURE 12.9

Equivalent Circuit for Calculating RTh

On the other hand, the value of ETh will be different for each different binary

input. It will be the sum of binary fractions of the full-scale output voltage, as previously

calculated for the generic DAC.

Similar analysis of the R-2R ladder shows that when b3b2b1b0 _ 0100, Va__Vref/4,

when b3b2b1b0 _ 0010, Va__Vref/8, and when b3b2b1b0 _ 0001, Va__Vref/16.

If two or more bits in the R-2R ladder are active, each bit acts as a separate voltage

source. Analysis becomes much more complicated if we try to solve the network as we did

for one active bit.

There is no need to go through a tedious circuit analysis to find the corresponding analog

voltage. We can simplify the process greatly by applying the Superposition theorem.

This theorem states that the effect of two or more sources in a network can be determined

by calculating the effect of each source separately and adding the results.

The Superposition theorem suggests a generalized equivalent circuit of the R-2R ladder

DAC. This is shown in Figure 12.10. A Thévenin equivalent source and resistance

corresponds to each bit. The source and resistance are switched in and out of the circuit,

depending on whether or not the corresponding bit is active.

N O T E

FIGURE 12.10

Equivalent Circuit of R-2R DAC

This model is easily expanded. The source for the most significant bit always has the

value Vref/2. Each source is half the value of the preceding bit. Thus, for a 5-bit circuit, the

source for the least significant bit has a value of Vref/32. An 8-bit circuit has an LSB equivalent

source of Vref/256.

❘❙❚ EXAMPLE 12.3 A 4-bit DAC based on an R-2R ladder has a reference voltage of 10 volts. Calculate the

analog output voltage, Va, for the following input codes:

a. 0000

c. 0100

a. Va__(0/16) Vref _ 0 V

b. Va__(8/16) Vref__(1/2) Vref__5 V

c. Va__(4/16) Vref__(1/4) Vref__2.5 V

d. Va__(12/16) Vref__(3/4) Vref__7.5 V

❘❙❚ EXAMPLE 12.4 Calculate the output voltage of an 8-bit DAC based on an R-2R ladder for the following input

codes. What general conclusion can be drawn about each code when compared to the

solutions in Example 12.3?

a. 00000000

b. 10000000

c. 01000000

d. 11000000