a. Output low characteristic

0.5

1

0 20 40 60

LS00

TA = 25C

VCC = 4.5 V

VO L , OUTPUT VOLTAGE (VOLTS)

0

4

3

1

–50 –100 –150

LS00 F00

VCC = 5.5 V

VO H , OUTPUT VOLTAGE (VOLTS)

FIGURE 11.10

Output Characteristics of 74LS00 and 74F00 Gate. Reprinted with permission of Motorola

In other words, a greater load in either state takes the output voltage further away from

its nominal value. This has an effect on other performance factors, such as noise margin,

which we will examine in a later section of the chapter.

The output voltage of a logic gate is defined in a datasheet for a particular value of

output current.

We will examine the fanout of CMOS devices in a later section on interfacing between

CMOS and TTL.

N O T E

❘❙❚ SECTION 11.3 REVIEW PROBLEM

11.3 The input and output currents IOH, IOL, IIH, and IIL of a TTL device may be classified

as source currents or sink currents. List each input or output current as a source or

sink current.

14.4 Power Dissipation

Power dissipation The electrical energy used by a logic circuit in a specified period

of time. Abbreviation: PD

currents.

power dissipation.

Electronic logic gates require a certain amount of electrical energy to operate. The measure

of the energy used over time is called power dissipation. Each of the different families of

logic has a characteristic range of values for the power it consumes.

For TTL and CMOS, the power dissipation is calculated as follows:

TTL: PD _ VCC ICC

High-Speed CMOS: PD _ VCC IT (IT _ quiescent _ dynamic supply

current)

Figure 11.11 shows the supply voltage and current in a 74XX00 NAND gate.

K E Y T E R M S

Vcc

Icc

Power Supply Voltage and

Current in a 74XX00

NAND gate.

The main difference between the two families is the calculation of supply current.

The supply current in a TTL device is different when its outputs are HIGH than when

they are LOW. Thus, supply current, ICC, and therefore power dissipation, depends on the

states of the device outputs. If the outputs are switching, ICC is proportional to output duty

cycle.

In a CMOS device, very little power is consumed when the device outputs are static.

Thus, the power dissipation of a device depends on the switching frequency of its

outputs.

11.4 • Power Dissipation 511

Power Dissipation in TTL Devices

Two values are given for supply current in a TTL data sheet. ICCL is the current drawn from

the power supply when all gate outputs are LOW. ICCH is the current drawn from the supply

when all outputs are HIGH. If the gate outputs are not all at the same level, the supply

current is the sum of currents given by:

H_ ICCH _ _

L_

ICCL

where

n is the total number of gates in the package

nH is the number of gates whose output is HIGH

nL is the number of gates whose output is LOW

The power dissipation of a TTL chip also depends on the duty cycle of the gate outputs.

That is, it depends on the fraction of time that the chip’s outputs are HIGH.

If we assume that, on average, the outputs of a chip are switching with a duty cycle of

50%, the supply current can be calculated as follows:

ICC _ (ICCH _ ICCL)/2

If the output duty cycle is other than 50%, the supply current is given by:

where DC _ duty cycle.

❘❙❚ EXAMPLE 11.8 Figure 11.12 shows a circuit constructed from the gates in a 74XX00 quadruple 2-input

NAND gate package. Use the data sheet shown in Figure 11.3 to determine the maximum

power dissipation of the circuit if the input is DCBA _ 1001 and the gates are 74LS00

NANDs. Refer to the data sheets in Appendix C and repeat the calculation for 74ALS00

and 74AS00 gates.

FIGURE 11.12

Power Dissipation of

74XX00 NAND

Solution

Gate 1:_AB _ 1

Gate 2:_CD _ 1

Gate 3: AB _ CD _ 0

Gate 4: _A_B_____C_D_ _ 1

Since three outputs are HIGH and one is LOW, the supply current is given by:

H_ ICCH _ _

L_

ICCL

_ _

3

4

1

4

Maximum supply current for each device is:

74LS00: ICC _ 0.75(1.6 mA) _ 0.25(4.4 mA) _ 2.3 mA

74ALS00: ICC _ 0.75(0.85 mA) _ 0.25(3 mA) _ 1.3875 mA

74AS00: ICC _ 0.75(3.2 mA) _ 0.25(17.4 mA) _ 6.75 mA

Maximum power dissipation for each device is:

74LS00: PD _ VCC ICC _ (5 V)(2.3 mA) _ 11.5 mW

74ALS00: PD _ VCC ICC _ (5V)(1.3875 mA) _ 6.94 mW

74AS00: PD _ VCC ICC _ (5V)(6.75 mA) _ 33.75 mW

(1 mW _ 1 milliwatt _ 10_3 W.)

❘❙❚ EXAMPLE 11.9 Find the maximum power dissipation of the circuit in Figure 11.12 if the gates are 74LS00

and the gate outputs are switching with an average duty cycle of 30%.

_ 3.56 mA

❘❙❚

CMOS gates draw the most power when their outputs are switching from one logic state to

the other. When the outputs are static (not switching), the large internal impedances of the

gate limit the supply current. A change of state requires the charging and discharging of internal

gate capacitances, resulting in a greater demand on the power supply current. Thus,

the faster a CMOS gate switches, the more current, and hence more power, it requires.

CMOS supply current has two components: a quiescent current that flows when the

gate is in a steady state and a dynamic component that depends on frequency. For relatively

high frequencies (about 1 MHz and up), the quiescent component is small compared to the

dynamic component and can be neglected.

The quiescent current is usually specified for an entire chip package, regardless of the

number of gates. It is given by ICC VCC. For a 74HC00A NAND gate, ICC _ 1 _A at room

temperature for a supply voltage of VCC _ 6.0 V. The dynamic component calculation accounts

for internal and load capacitance and is given, per gate, by:

(CL _ CPD) V2

CC f

where CL is the gate load capacitance

CPD is the gate internal capacitance

VCC is the supply voltage

f is the switching frequency of the gate output

❘❙❚ EXAMPLE 11.10 The circuit in Figure 11.12 is constructed from 74HC00A high-speed CMOS NAND gates.

Calculate the power dissipation of the circuit:

a. When the gate inputs are steady at the state DCBA _ 1010

b. When the outputs are switching at an average frequency of 10 kHz

c. When the outputs are switching at an average frequency of 1 MHz

Supply voltage is 5 V. Temperature range is 25°C to _55°C.

11.4 • Power Dissipation 513

Solution Refer to the 74HC00A data sheet in Appendix C.

a. PD _ VCC ICC _ (5 V)(1 _A) _ 5 _W. This is the quiescent power dissipation of the

circuit.

b. The 74HC00A data sheet indicates that each gate has a maximum input capacitance, Cin

of 10 pF. Assume that this value represents the load capacitance of gates 1, 2, and 3 of

the circuit in Figure 11.12. Further assume that gate 4 has a load capacitance of 0. The

total power dissipation of the circuit is given by:

PD _ 3(22 pF _ 10 pF)(5 V)2 (0.01 MHz)

_ (22 pF)(5 V)2 (0.01 MHz) _ 5 _W

_ 3(8 _W) _ 5.5 _W _ 5 _W

_ 34.5 _W

c. For f _ 1 MHz, total power dissipation is given by:

PD _ 3(22 pF _ 10 pF)(5 V)2 (1 MHz)

_ (22 pF)(5 V)2 (1 MHz) _ 5 _W

_ 3(800 _W) _ 550 _W _ 5 _W

_ 2955 _W _ 2.95 mW

❘❙❚ EXAMPLE 11.11 The circuit in Figure 11.12 is constructed using a 74LS00 quad 2-in NAND gate and again

with a 74HC00 quad 2-in NAND. Both circuits have identical waveforms applied to their

inputs that make all gate outputs switch with a duty cycle of 50%. Calculate the frequency

at which the power dissipation of the 74HC00 circuit exceeds that of the 74LS00 circuit.

Assume VCC _ 5 V and temperature _ 25°C for both circuits.

Solution The power dissipation of the LSTTL circuit is:

PD _ VCC ICC _ (VCC) (ICCH _ ICCL)/2 _ (5V) (1.6 mA _ 4.4 mA)/2

_ (5 V) (3.0 mA) _ 15 mW

Neglect the quiescent current of the high-speed CMOS circuit.

Per gate: PD _ (CL _ CPD)VCC

2 f

CPD _ 22 pF per gate

CL _ 10 pF for 3 gates and 0 pF for 1 gate

Total: PD _ (3(10pF _ 22 pF) _ 22 pF)(5 V)2f

_ (3(32 pF) _ 22 pF) (25 V2) f

_ (96 pF _ 22 pF) (25 V2) f _ (118 pF) (25 V2) f

For PD _ 15 mW:

f __

(118

p

5

m

)(

25V2) _ _ 5.08MHz

The power dissipation of the 74HC00 circuit exceeds that of the 74LS00 circuit at 5.08

MHz.

The power saving in a high-speed CMOS circuit generally results from the fact that

most device outputs are not switching at any given time. The power dissipation of a

TTL circuit is independent of frequency and therefore draws some power at all

times. This is not the case for CMOS, which draws the majority of its power when

switching.

N O T E

514 C H A P T E R 1 1 • Logic Gate Circuitry

❘❙❚ SECTION 11.4 REVIEW PROBLEM

11.4 Why does CMOS power dissipation increase with frequency?

11.5 Noise Margin

Electrical circuits are susceptible to noise, or unwanted electrical signals. Such signals

are often induced by electromagnetic fields of motors, fluorescent lighting, highfrequency

electronic circuits, and cosmic rays. They can cause erroneous operation of a

digital circuit. Since it is impossible to eliminate all noise from a circuit, it is desirable

to build a certain amount of tolerance, or noise margin, into digital devices used in the

circuit.

In all circuits studied so far, we have assumed that logic HIGH is _5 volts and logic

LOW is 0 volts in devices with a 5-volt supply. In practice, there is a certain amount of

tolerance on both the logic HIGH and LOW voltages; for TTL devices, a HIGH at a device

input is anything above about _2 volts, and a LOW is any voltage below about _0.8

volts. Due to internal voltage drops, the HIGH output of a TTL gate is typically about

_3.5 volts.

Figure 11.13 shows one inverter driving another. In Figure 11.13a, the output of the

first inverter and the input of the second have the same logic threshold. That is, the input

of the second gate recognizes any voltage above 2.7 volts as HIGH (VIH _ 2.7 V) and

any voltage below 0.5 volts as LOW (VIL _ 0.5 V). The output of the first inverter produces

at least 2.7 volts when HIGH (VOH _ 2.7 V) and no more than 0.5 volts as LOW

(VOL _ 0.5 V).

If there is noise on the line connecting the two gates, it will likely cause the voltage of

the second gate input to penetrate into the forbidden region between logic HIGH and LOW

levels. This is shown on the graph of the waveform in Figure 11.13a. When the voltage enters

the forbidden region, the gate will not operate reliably. Its output may switch states

when it is not supposed to.

Figure 11.13b shows the same circuit with different logic thresholds at input and output.

The output of the first inverter is guaranteed to be at least 2.7 volts when HIGH (VOH_

2.7V) and no more than 0.5 volts when LOW (VOL _ 0.5 V). The second gate recognizes

any input voltage greater than 2 volts as a HIGH (VIH _ 2 V) and any input voltage less

The difference between logic thresholds allows for a small noise voltage, equal to or

less than the difference, to be superimposed on the desired signal. It will not cause the input

voltage of the second inverter to penetrate the forbidden region. This ensures reliable

operation even in the presence of some noise.

For the 74LS04 inverter, the HIGH-state and LOW-state noise margins, VNH and

A device with these values of VIH and VIL is deemed to be TTL compatible.

K E Y T E R M S

11.5 • Noise Margin 515

❘❙❚ EXAMPLE 11.12 Use the 74HC00A data sheet in Appendix C to calculate the noise margins for this gate.

Assume VCC _ 4.5 V, ambient temperature (TA) is 25°C, and the driving gate is fully

loaded (IOUT_ 4 mA).

❘❙❚

LOW

GATE 1 OUTPUT

5 V

VOH _ 2.7 V

0 V

LOW

GATE 2 INPUT

5 V

A, volts

V0H_

V0L

VIL _ 0.5 V

0 V

t

FORBIDDEN

HIGH

5 V

VOL _ 0.5 V

0 V

FORBIDDEN

HIGH

5 V

VIH _ 2.0 V

V0H

VNH

VIH

VIL _ 0.8V VIL

0 V

t

Noise pushes VIH, VIL

Noise within specs for VIH, VIL

A 1 2

A A

Noise Margins

❘❙❚ SECTION 11.5 REVIEW PROBLEM

11.5 Calculate the noise margins of a 74HCT00A NAND gate from the data sheet in Appendix

C. VCC _ 4.5 V, TA _ 25°C, IOUT_ 4 mA

voltage compatibility with TTL.

Interfacing different logic families is just an extension of the fanout and noise margin problems;

you have to knowwhat the load gates of a circuit require and what the driving gates can

supply. In practice, this means you must know the specified values of input and output voltages

and currents for the gates in question. Table 11.4, which is derived from the manufacturers’data

sheets included inAppendix C, gives an overviewof input and output parameters

for a variety of TTL and CMOS families. Ambient temperature is assumed to be 25°C.

K E Y T E R M

Table 11.4 TTL and CMOS Input and Output Parameters

Low-Voltage

TTL High-Speed CMOS CMOS

74LS 74F 74AS 74ALS 74HC 74HCT 74VHC 74VHCT 74LVX 74LCX

VCC (V) 5.0 5.0 5.5 5.5 4.5 4.5 4.5 4.5 3.0 3.0

VOH (V) 2.7 2.7 3.0 3.0 3.98 3.98 3.94 3.94 2.58 2.2

VOL (V) 0.5 0.5 0.5 0.5 0.26 0.26 0.36 0.36 0.36 0.55

VIH (V) 2.0 2.0 2.0 2.0 3.15 2.0 3.15 2.0 2.0 2.0

VIL (V) 0.8 0.8 0.8 0.8 1.35 0.8 1.35 0.8 0.8 0.8

IOH (mA) _0.4 _1.0 _2.0 _0.4 _4.0 _4.0 _8.0 _8.0 _4.0 _24.0

IOL (mA) 8.0 20.0 20.0 8.0 4.0 4.0 8.0 8.0 4.0 24.0

IIH (mA) 0.02 0.1 0.02 0.02 0.0001 0.0001 0.0001 0.0001 0.0001 0.0001

IIL (mA) _0.4 _0.6 _0.5 _0.1 0.0001 0.0001 0.0001 0.0001 0.0001 0.0001

Table 11.4 is useful for comparison of logic families, but it is not a substitute for reading

data sheets, as it gives parameters only under a restricted set of conditions. We can,

however, make some observations based on the data in Table 11.4.

1. Input currents in a CMOS gate are very low, due to its high input impedance. As a result

fanout is generally not a problem with CMOS loads. Interface problems to CMOS loads

have to do with input voltage, not current.

2. CMOS devices, such as 74HCT, that have the same values of VIH and VIL as the TTL

families in Table 11.4, are considered to be TTL compatible, since they can be driven

directly by TTL drivers.

3. LSTTL is usually regarded as the benchmark for measuring TTL loading of a CMOS

circuit. For example, a data sheet will claim that a device can drive 10 LSTTL loads.

This claim depends on the values of IOH and IOL for the driving gate, which are not

listed directly in CMOS data sheets, except as absolute maximum ratings. The values in

Table 11.4 are the values of current for which the output voltages, VOH and VOL, are defined.

(Recall from the section on fanout in this chapter that increasing output current

causes output voltages to migrate away from their nominal values, thus reducing device

noise margins.)

Let us examine four interfacing problems: high-speed CMOS driving 74LS, 74LS driving

74HC, 74LS driving 74HCT, and 74LS driving low-voltage CMOS.

High-Speed CMOS driving 74LS

To design an interface between any two logic families, we must examine the output voltages

and currents of the driving gate and the input voltages and currents of the load gates.

Assume a 74HC00 NAND gate drives one or more 74LS00 NAND gates. From the

74HC00 data sheet, we determine that VOH _ 3.98 V and VOL _ 0.26 V for VCC _ 4.5 V.

The 74LS00 requires at least 2.0 V at its input in the HIGH state and no more than 0.8 V in

the LOW state. The 74HC00 therefore satisfies the input voltage requirement of the

74LS00.

For the defined output voltages, the 74HC00 gate can source or sink 4 mA. The fanout

O

IH

_ _

4

0

_

A

_ 200

O

IL

_ _

0

m

A_

_ 10

Therefore a 74HC00 NAND can drive a 74LS00 directly, with a fanout of 10.

74LS Driving 74HC

As mentioned earlier, CMOS has a very small input current and therefore does not present

a fanout problem to a 74LS driving gate. However, we must also examine the interface for

voltage compatibility.

From data sheets, we see that a 74LS00 gate is guaranteed to provide at least 2.7 V in

the HIGH state and no more than 0.5 V in the LOW state. A 74HC00 gate will recognize

anything less than 1.35 V as a logic LOW and anything more than 3.15 V as a logic HIGH.

The 74LS00 meets the LOW-state criterion, but it cannot guarantee sufficient output voltage

in the HIGH state.

In order to properly drive a 74HC input with a 74LS output, we must provide a pull-up

resistor to ensure sufficient HIGH-state voltage at the 74HC input. The circuit is illustrated

in Figure 11.14. The pull-up resistor should be between 1 k_ and 10 k_.

Vcc

Rp

GND

74HC00

LSTTL driving 74HC CMOS

74LS Driving 74HCT

74HCT inputs are designed to be compatible with TTL outputs. As with 74HC devices, input

currents are sufficiently low that fanout is not a problem with the 74LS-to-74HCT interface.

74HCT input voltages are the same as those for TTL (VIH_2.0V and VIL_0.8V).

Therefore, 74HCT inputs can be driven directly by LSTTL outputs.

74LS Driving Low-voltage CMOS

CMOS families with supply voltages less than 5 V are rapidly becoming popular in new

applications. Two of the reasons for their increasing prominence are reduced power dissipation

(inversely proportional to the square of the supply voltage) and smaller feature size