Test Technology Standards Committee Update Rohit Kapur Mar 2008 Attendees

VTS meeting is yet to occur.

None – as it occurs at the VTS meeting

1149.1-2001 (C/TT) Reaffirmation "IEEE Standard Test Access Port and Boundary Scan Architecture" will be reviewed by RevCom for its 26 March 2008 meeting.   RevCom preliminary comments will be sent to you in mid-March 2008.

A parser has been developed to check the proposed BSDL extensions’ syntaxes and rules. The group is currently reviewing the whole standard documentation to identify any information that needs to be enhanced or corrected. The group meeting minutes are available at http://grouper.ieee.org/groups/1149/4/index.html.

The P1149.7 working group, Reduced-pin and Enhanced-functionality Test Access Port and Boundary Scan Architecture, is completing its final draft specification review.  We are focusing our review on rules clarification.  The WG met face to face four times in 2007, with the next F2F scheduled for mid March.  The team continues to hold bi-weekly teleconferences as well as "full day" meetings to review the clause material.  Balloting is now planned for later in the summer, depending on the completion of the rules review.   We continue to communicate with external parties concerning compliance validation for this proposed standard, and we continue to participate in industry conferences to promote this technology.  The WG is also looking for interested parties to review the current clause material and provide feedback to the group.

1450.3 (TRC) - is complete and can now be ordered directly from IEEE. Apparantly it is not yet on the directly downloadable list of pdfs on the IEEE web site. The working group has now gone into full dormant mode - no meetings, no plans.

The 1450.4 working group has taken measures to put a "full court press" on efforts to complete this standard in 2008.  We have restructured the working group into sub-teams which will address separate work items and bring them back to the full team for review and approval at frequent intervals.  We have paired down our work items into a prioritized to do list.  We are focusing on the highest priority work items which we have determined are "must have" for this standard to go to ballot.  We have also increased our weekly full team meeting duration time from 60 to 90 minutes which has helped us to make good progress with the extra time being focused on the context of the discussions at hand.  The team is also putting more energies into the working group process and we will be putting a project plan in place to help ensure success towards our end goal this year.  Also, we are moving to an MS Word format for the documentation which will help facilitate better back and forth of work products for the sub-teams and the master document.  Recent efforts have made good progress on binning constructs for the dot4 standard.

A requested two year extension for the P1581 PAR has been approved by the IEEE. The group is working on a demo board which is be used to demonstrate the P1581 features and capabilities. A demonstration of the principles has been completed for an SRAM type device. Next, additional demos will be created for NOR Flash and NAND Flash devices. The working group holds monthly conference calls and is trying to solicit participation and/or feedback from the memory device manufacturer community.

The Chair (Ken Posse), Vice Chair (Al Crouch), and Editor (Jeff Rearick) remain as before.  However, the Working Group has enjoyed a number of new additions thus improving our expertise level with respect to EDA systems, test systems, and ASIC/processor design.

The team has completed its technical work and has started writing the document. Moving towards ballot in the near future.

Good progress is made across all sub teams.  There is a general agreement on the Memory CTL to be structured into different CTL blocks.

 The redundancy and repair team is very active. Have several meetings to accelerate the definition on the block.

 The memory access team is a little bit behind. Team leaders and members are not able hold meetings lately. This should be addressed in March.
 We have two new members, one from ST Micro Electronics and one from NXP.

 The web page is up to date with all the meetings minutes and documents under discussion.

 A one page summary on the standard is under preparation to be included in the special issue of Design&Test magazine on Core Based testing.
 We are planning to have a face to face meeting at VTS08 in San Diego on April 28.  

 At that meeting will have a better visibility on the different Milestones.

STDF scan fail datalog standardization working group is close to completing the first draft of the standard for the scan fail datalog. The memory fail datalog working is currently focusing on the embedded memory fail data collection requirements and reviewing some early proposals.

At the 2003 meeting of SJTAG at ITC, the members voted to use the PICMG Advanced Telecommunications Computing Architecture (ATCA) standards organization system specification as a primary case study to support JTAG at the system level where there was no availability of JTAG on the backplane.  The PICMG organization has changed its position recently regarding the use of JTAG at the system level and is now considering adding JTAG to the backplane definition. Continuing our efforts to understand how boundary-scan is used at the system level, a sub-committee, formed to analyze the ATCA change request for adding JTAG support into the next release of the PICMG Advance Telecommunications Computing Architecure (ATCA) standard, has been meeting weekly to define and discuss various use cases for JTAG at the system level.  We are confident the analysis and proposed white paper on the results will provide enough of a framework to begin to establish consensus of the goals and objectives for the SJTAG effort so we may proceed with the formation of a PAR and become an official IEEE working group with a number associated with this effort.

Thanks to Ian McIntosh, one of our most active members, we have a new SJTAG web site allowing Ben Bennetts to officially retire from hosting our support site.  The new web site may be accessed at:  http://www.sjtag.org.  On this site, we are posting the current white papers, transcripts of our meetings, and forums to capture various discussion points relating to SJTAG.  Many people from industry have been accessing this site and are following the progress being made by the group.  Members of the PICMG ATCA working group have also been monitoring our progress through this site.

Members from our team have also been active on the P1687, P1581, and P1149.7 working groups to ensure compatibility of the direction of SJTAG with these standards efforts.

The working group was mostly inactive during the year.  There were 2 email discussions:  Errata/corrigendum to dot 1 for associated, observe-only cell; proposed "robust" test receiver with DC edge detection.  Both of these issues will be discussed at the upcoming 1149.6 meeting.

1532 is happily coasting along.  I believe this year we are up for reaffirmation.  I need to dust the cobwebs off the team and get moving on this in the next few months.

The group has been inactive. A search is needed for a new Chair. TTSG will discuss this issue to determine the next steps for this activity.

 

Proposal for a Probe Card Standard (Bernie West)

No progress due to lack of time. Since no progress was made by VTS 2007 this activity will be ceased. Discussion at ITC 2007 meeting on this subject if Bernie attends.

Die Products Consortium (DPC) membership reached consensus on a specific counting methodology for the stuck-at faults. DPC sponsored Texas A&M to develop a Fault Counting tool based on the agreed upon methodology. The tool has been used by various DPC member companies on their designs and the tool is now available for use by DPC members. The methodology is in alignment with JEDEC standards on Test Coverage Reporting for applications supported by Automotive Electronics Council (AEC). The current version of Fault Counting is limited to Stuck-At fault model and limited to faults on cell boundaries. The expectation is to build the methodology to cover internal faults and also provide counting methodology for the advanced fault models. In order to make Fault counting methodology an industry standard, DPC membership now needs to solicit wider participation (perhaps with help from IEEE Stds Body).