Chapter 1 Basic Principles of Digital Systems outlin e 1
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Logic Array Logic Array Block (LAB) Logic Element (LE) Local Interconnect Embedded Array Embedded Array Block (EAB) I/O Element (IOE) Column
Interconnect Row
Interconnect Logic
Array EAB
EAB FIGURE 8.27 FLEX10K Device Block Diagram (Courtesy of Altera) ❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚ S U M M A R Y ries of programmable AND/OR circuits, and look-up table (LUT), that stores the truth table of a Boolean function in a small memory. 2. Programmable array logic (PAL) is an SOP-type architecture in which there are a series of programmable AND gates that have a fixed connection to an OR-gate output. 3. Connections from PLD inputs to PAL AND arrays were historically made by leaving intact selected fuses in a crosspoint fuse array. In modern PLDs, these connections are made by programming EEPROM (electrically erasable programmable read only memory) cells. 4. An AND-gate input in a PAL array is called a product line. 5. A PAL16L8 PLD is an SOP device with up to 16 inputs and up to 8 outputs. There are 10 dedicated inputs, 2 dedicated outputs, and 6 pins that can be configured as input or output. All outputs in the PAL16L8 are active-LOW. 6. A PAL is programmed by a computer and programming hardware that uses a JEDEC file as a template for determining which fuses to blow and which to leave intact. 7. Some PAL devices have programmable-polarity outputs. This is achieved with an XOR gate that has a programmable cell or fuse on one input to switch the output between inverting and noninverting levels. 8. A registered PLD output consists of a flip-flop (usually D-type) on the output of an SOP matrix. 9. A PAL part number indicates the number of registered outputs (e.g., a PAL16R8 has eight registered outputs). 10. Early-version standard PALs are limited in that they are one-time programmable (OTP), their outputs are permanently configured as combinational or registered, and they cannot be programmed in-system. Later-version PALs (e.g., PAL16CE16V8 Universal PAL) and GALs (generic array logic such as GAL22V10) overcome these limitations. 11. PALs and GALs with configurable architecture have outputs that can be combinational or registered, with various input or
21. If the ISP capability of a CPLD is to be used, there are four fewer pins available on the CPLD for user I/O. 22. Each MAX7000S macrocell has five dedicated product lines and capability to borrow or share additional product terms with neighboring macrocells in the same LAB. 23. Shared logic expanders allow one product term per macrocell to be shared with other macrocells in the LAB, totaling 16 product terms per LAB. The expander inverts the product term and feeds it back into the LAB AND matrix. 24. Parallel logic expanders allow a macrocell to borrow product lines from neighboring macrocells. These borrowed product lines are only available to one macrocell. 25. Expander assignments are done automatically by MAX_ PLUS II at compile time. 26. MAX7000S devices are based on EEPROM cells and are thus nonvolatile. 27. The Altera FLEX10K series of CPLDs is based on a look-up table (LUT) architecture. A look-up table consists of a 16-bit array of storage elements that are selected by four logic inputs.
28. An LUT combined with switching, configuration, and expansion circuitry comprises a logic element (LE), whose function is equivalent to a macrocell in an SOP-type device. 29. Eight logic elements and a local interconnect make up a Logic Array Block (LAB). 30. LABs in a FLEX10K device are interconnected by global row and column busses. 31. The number of inputs in a logic function can be expanded beyond the capacity of one logic element by using cascade chains. 32. Carry chains can be used to more efficiently implement carry functions in adders, counters, and comparators. 33. FLEX10K devices are based on SRAM technology and are therefore volatile; they must be reconfigured each time power is applied to the circuit. feedback options. 12. Configurable output circuits in a PLD are called output logic macrocells (OLMCs) or just macrocells. 13. Macrocells are configured by programming architecture cells. Global architecture cells affect all macrocells in a device. A local architecture cell affects only the macrocell in which it is found. 14. GALs and Universal PALs have global control signals, such as clock, clear, and output enable, that can be applied to all macrocells in the device. 15. A GAL22V10 has ten macrocells, a global clock that can be used as a combinational input for nonclocked designs, and eleven dedicated inputs. 16. The GAL22V10 macrocells are not all the same size. There are two macrocells with each of the following numbers of product terms: 8, 10, 12, 14, 16. 17. PLDs that can be programmed while installed in a circuit are called in-system programmable (ISP). They are programmed by a 4-wire interface that complies to a standard published by the Joint Test Action Group (JTAG) and the IEEE (Std. 1149.1).
18. An Altera MAX7000S CPLD consists of groups of 16 macrocells, called Logic Array Blocks (LABs), that are interconnected by an internal bus called a Programmable Interconnect Array (PIA). 19. The number of macrocell outputs in an LAB that are connected to I/O pins depends on the CPLD package type. Macrocells that do not have external connections can still be used for buried logic function. 20. MAX7000S devices have four programmable control pins: global clock (GCLK1), Global Output Enable (OE1), Global Clear (GCLRn), and a pin that can be configured as a second global clock (GCLK2) or as a second global output enable (OE2). If these functions are not used, the associated pins can be used as standard I/Os. 21. If the ISP capability of a CPLD is to be used, there are four fewer pins available on the CPLD for user I/O. G L O S S A R Y
with other architecture cells, sets the configuration of a macrocell. Buried logic Logic circuitry in a PLD that has no connection to the input or output pins of the PLD, but is used solely as internal logic.
operation of carry functions between logic elements. Cascade chain A circuit in a CPLD that allows the input width of a Boolean function to expand beyond the width of one logic element.
by the intersection of an input line and a product line. Checksum An error-checking code derived from the accumulating sum of the data being checked. CPLD Complex programmable logic device. A programmable logic device consisting of several interconnected programmable blocks.
elements in a CPLD (2048 bits in a FLEX10K device), used for implementing complex logic functions in look-up table format.
whose outputs can be configured as combinational or registered and whose programming matrix is based on electrically erasable logic cells. Global architecture cell An architecture cell that affects the configuration of all macrocells in a device. Global clock A clock signal in a PLD that clocks all registered outputs in the device. I/O Control Block A circuit in an Altera CPLD that controls the type of tristate switching used in a macrocell output. Input line A line which applies the true or complement form of an input variable to the AND matrix of a PLD. Input line number A number assigned to a true or complement input line in a PAL AND matrix. Problems 361
programmed through a standard four-wire interface while installed in a circuit.
which fuses are blown and which are intact in a programmable logic device.
Action Group (JTAG) used for loading test data or programming data into a PLD installed in a circuit.
configuration of one macrocell only. Logic Array Block (LAB) A group of macrocells that share common resources in a CPLD. Logic element (LE) A circuit internal to a CPLD used to implement a logic function as a look-up table. Look-up table (LUT) A circuit that implements a combinational logic function by storing a list of output values that correspond to all possible input combinations.
be directed to a single output. One-time programmable (OTP) A property of some PLDs that allows them to be programmed, but not erased. Output logic macrocell (OLMC) An input/output circuit that can be programmed for a variety of input or output configurations, such as active HIGH or active LOW, combinational, or registered. Often just called a macrocell. PAL Programmable array logic. Programmable logic with a fixed OR matrix and a programmable AND matrix. Parallel logic expanders Product terms that are borrowed from neighboring macrocells in the same LAB. Product line A single line on a logic diagram used to represent all inputs to an AND gate (i.e., one product term) in a PLD sum-of-products array.
particular product line in a PAL AND matrix where all cells are consecutively numbered.
with programmable connections that link together the Logic Array Blocks of a CPLD.
function can be programmed by the user, usually in sum-ofproducts form.
or more bits of digital information. Registered output An output of a programmable array logic (PAL) device having a flip-flop (usually D-type) which stores the output state.
fed back into the programmable AND matrix of an LAB for use by any other macrocell in the LAB.
disk.
Universal PAL A PLD based on erasable cells and configurable outputs, much like GAL, but primarily designed to emulate PAL devices, such as PAL16L8. P R O B L E M S Problem numbers set in color indicate more difficult problems; those with underlines indicate most difficult problems. Section 8.1 Introduction to Progammable Logic Section 8.2 PAL Fuse Matrix and Combinational Outputs
Section 8.3 PAL Outputs With Programmable Polarity 8.1 Draw a diagram showing the basic configuration and symbology for a PLD sum-of-products array. 8.2 Draw a basic PAL circuit having four inputs, eight product terms, and one active-LOW combinational output. Draw fuses on your diagram showing how to make the following Boolean expression: F_ _ A_ B C_ _ B_ C D _ A_ C D _ A C_ D 8.3 Modify the PAL circuit drawn in Problem 8.2 to make two outputs having eight product terms and programmable polarity. Draw fuses on the diagram for each of the following functions: F1 _ A B C_ _ _B C D _ A_ C D _ A C_ D F_2_ _ A_ B C_ _ B_ C D _ A_ C D _ A C_ D 8.4 Make a photocopy of Figure 8.8 (PAL20P8 logic diagram). Draw fuses on the PAL20P8 logic diagram showing how to make a BCD-to-2421 code converter, as developed in Example 3.22. Table 8.3 shows how the two codes relate to each other. The equations are listed on page 362. Table 8.3 BCD and 2421 Code Decimal BCD Code 2421 Code Equivalent D4 D3 D2 D1 Y4 Y3 Y2 Y1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 2 0 0 1 0 0 0 1 0 3 0 0 1 1 0 0 1 1 4 0 1 0 0 0 1 0 0 5 0 1 0 1 1 0 1 1 6 0 1 1 0 1 1 0 0 7 0 1 1 1 1 1 0 1 8 1 0 0 0 1 1 1 0 9 1 0 0 1 1 1 1 1
The Boolean equations for the BCD-to-2421 decoder are:
following PAL devices: a. PAL16R4 b. PAL16R6 c. PAL16R8
to a PAL16L8. 8.9 State the difference between a global architecture cell and a local architecture cell in a PALCE16V8. 8.10 How many macrocells are there in a GAL22V10? How many product lines do these macrocells have? 8.11 State the four configurations possible with a macrocell in a GAL22V10. 8.12 Is there a global output enable function available for a PALCE16V8? For a GAL22V10? 8.13 Can the registered outputs of a PALCE16V8 be clocked by a product term function from the PAL AND matrix? 8.14 Can the registered outputs of a GAL22V10 be clocked by a product term function from the GAL AND matrix? 8.15 Are the Asynchronous Reset (AR) and Synchronous Preset (SP) functions in a GAL22V10 global or local? Explain your answer in one sentence.
Altera MAX7000S, differs from a low-density PAL or GAL.
CPLDs:
a. EPM7032 b. EPM7064 c. EPM7128S d. EPM7160S 8.18 Which of the CPLDs listed in Problem 8.17 are in-system programmable? What does it mean when a device is insystem programmable?
MAX7000S CPLD? 8.20 How many user I/O pins are there in an EPM7128SLC84 CPLD? How many pins per LAB does this represent? 8.21 What can be done with the macrocells in an LAB that do not connect to I/O pins? 8.22 State the possible clock configurations of a MAX7000S macrocell. 8.23 State the possible reset configurations of a MAX7000S macrocell. 8.24 State the possible preset configurations of a MAX7000S macrocell. 8.25 How many dedicated product terms are available in a MAX7000S macrocell? How can this number of product terms be supplemented? What is the maximum number of product terms available to a macrocell? 8.26 How many shared logic expanders are available in an LAB?
8.7 FLEX10K CPLD 8.27 Briefly state the difference between CPLDs having sumof- products architecture and look-up table architecture. 8.28 How many inputs can a look-up table accept in an Altera FLEX10K logic element? How can this be expanded? 8.29 What is the purpose of the carry chain in a FLEX10K CPLD?
8.30 How many logic elements are there in a FLEX10K LAB? 8.31 How many bits of storage are there in an Embedded Array Block in a FLEX10K CPLD? 363 ❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚ ❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚
Counters and Shift Registers O U T L I N E
Digital Counters 9.2 Synchronous Counters
9.3 Design of Synchronous Counters
Binary Counters in VHDL
Synchronous Counters
Presettable and Bidirectional Counters in VHDL 9.7 Shift Registers 9.8 Programming Shift Registers in VHDL 9.9 Shift Register Counters
C H A P T E R O B J E C T I V E S Upon successful completion of this chapter you will be able to: • Determine the modulus of a counter. • Determine the number of outputs required by a counter for a given modulus. • Determine the maximum modulus of a counter, given the number of circuit outputs. • Draw the count sequence table, state diagram, and timing diagram of a counter. • Determine the recycle point of a counter’s sequence. • Calculate the frequencies of each counter output, given the input clock frequency. • Draw a circuit for any full sequence synchronous counter. • Determine the count sequence, state diagram, timing diagram, and modulus of any synchronous counter. • Complete the state diagram of a synchronous counter to account for unused states. • Design the circuit of a truncated sequence synchronous counter, using flipflops and logic gates. • Use MAX_PLUS II to create a graphic design file for any synchronous counter circuit. • Use behavioral descriptions in VHDL to design synchronous counters of any modulus. • Use a parameterized counter from the Library of Parameterized Modules in a VHDL file. • Use the MAX_PLUS II simulation tool to verify the operation of synchronous counters. • Implement various counter control functions, such as parallel load, clear, count enable, and count direction, both in Graphic Design Files and in VHDL.
• Design a circuit to decode the output of the counter, both in a MAX_PLUS II Graphic Design File or in VHDL. • Draw a logic circuit of a serial shift register and determine its contents over time given any input data. 364 C H A P T E R 9 • Counters and Shift Registers Counters and shift registers are two important classes of sequential circuits. In the simplest terms, a counter is a circuit that counts pulses. As such, it is used in many circuit applications, such as event counting and sequencing, timing, frequency division, and control. A basic counter can be enhanced to incorporate functions such as synchronous or asynchronous parallel loading, synchronous or asynchronous clear, count enable, directional control, and output decoding. In this chapter, we will design counters using schematic entry, VHDL, and counters from the Library of Parameterized Modules and verify their operation using the MAX_PLUS II simulator. Shift registers are circuits that store and move data. They can be used in serial data transfer, serial/parallel conversion, arithmetic functions, and delay elements. As with counters, many shift registers have additional functions such as parallel load, clear, and directional control. We can implement these circuits using schematic entry, VHDL, and LPM components. _ 9.1 Basic Concepts of Digital Counters Counter A sequential digital circuit whose output progresses in a predictable repeating pattern, advancing by one state for each clock pulse. Recycle To make a transition from the last state of the count sequence to the first state.
Count sequence The specific series of output states through which a counter progresses. State diagram A diagram showing the progression of states of a sequential circuit.
Modulus The number of states through which a counter sequences before repeating. Modulo-n (or mod-n) counter A counter with a modulus of n. UP counter A counter with an ascending sequence. DOWN counter A counter with a descending sequence. K E Y T E R M S • Draw a timing diagram showing the operation of a serial shift register. • Draw the logic circuit of a general parallel-load shift register. • Draw a timing diagram showing the operation of a parallel-load shift register. • Draw the general logic circuit of a bidirectional shift register and explain the concepts of right-shift and left-shift. • Use timing diagrams to explain the operation of a bidirectional shift register. • Describe the operation of a universal shift register. • Design shift registers, ring counters, and Johnson counters with the MAX_PLUS II Graphic Editor or VHDL. • Verify the operation of shift registers, ring counters, and Johnson counters using the MAX_PLUS II simulation tool. • Design a decoder for a Johnson counter. • Use a ring counter or a Johnson counter as an event sequencer. • Compare binary, ring, and Johnson counters in terms of the modulus and the required decoding for each circuit.
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