FIGURE 7.64 Timing Parameters of a JK Flip-Flop 314 C H A P T E R 7 •

Timing Parameters of a JK Flip-Flop

The timing restrictions of a flip-flop imply that there is a maximum CLK frequency beyond

which the device will not operate reliably. Data sheets give these values as about 30

MHz for both LSTTL and high-speed CMOS devices.

Table 7.11 summarizes the timing parameters of a 74LS107A flip-flop and a 74HC107

device. The values for the latter device are for Vcc _ 4.5 V and a temperature range of

_55°C to 25°C; they increase with a higher temperature range or a lower supply voltage.

Table 7.11 Timing Parameters of an LSTTL and a High-Speed

CMOS Flip-Flop

(from CLK) 20 ns 25 ns

❘❙❚ EXAMPLE 7.11 The timing diagrams in Figure 7.65 represent some of the timing parameters of a JK flipflop.

From these diagrams, determine the setup and hold times and the propagation delays

from CLK and C_L_R_ to Q and Q_.

Example 7.11

Timing Parameters

SOLUTION The values are as follows:

Setup time _ 15 ns

Hold time _ 5 ns

Propagation delays (from CLK): 25 ns (tpLH and tpHL)

(from C_L_R_): 20 ns(tpLH and tpHL)

Summary 315

❘❙❚ SECTION 7.7 REVIEW PROBLEM

7.7 An active edge on the clock input of a JK flip-flop makes Q go from HIGH-to-LOW.

Name the timing parameter that measures the delay between the input and output

change. Write the symbol for the parameter.

S U M M A R Y

1. A combinational circuit combines inputs to generate a particular

output logic level that is always the same, regardless of

the order in which the inputs are applied. A sequential circuit

might generate different outputs for the same inputs, depending

on the sequence in which the inputs were applied.

2. An SR latch is a sequential circuit with SET (S) and RESET

(R) inputs and complementary outputs (Q and Q_). By definition,

a latch is set when Q _ 1 and reset when Q _ 0.

3. A latch sets when its S input activates. When S returns to the

inactive state, the latch remains in the set condition until explicitly

reset by activating its R input.

4. A latch can have active-HIGH inputs (designated S and R) or

active-LOW inputs (designated S_ and R_).

5. Two basic SR latch circuits are the NAND latch and the

NOR latch, each consisting of two gates with cross-coupled

feedback. In the NAND form, we draw the gates in their

DeMorgan equivalent form so that each circuit has ORshaped

gates, inversion from input to output, and feedback to

the opposite gate.

6. A NOR latch has active-HIGH inputs. It is described by the

following function table:

9. A gated SR latch controls the times when a latch can switch.

The circuit consists of a pair of latch gates and a pair of steering

gates. The steering gates are enabled or inhibited by a

control signal called ENABLE. When the steering gates are

enabled, they can direct a set or reset pulse to the latch gates.

When inhibited, the steering gates block any set or reset

pulses to the latch gates so the latch output cannot change.

10. A gated D (“data”) latch can be constructed by connecting

opposite logic levels to the S and R inputs of an SR latch.

Since S and R are always opposite, the D latch has no forbidden

state. The no change state is provided by the inhibit

property of the ENABLE input.

11. In a gated D latch (or transparent latch), Q follows D when

When ENABLE is inactive, the latch stores the last value of D.

12. A D latch can be described in VHDL by an IF statement

within a PROCESS. The PROCESS statement in VHDL is

concurrent, but the statements inside the PROCESS are sequential.

13. A D latch can also be implemented in VHDL by instantiating

a LATCH primitive as a component in a VHDL design entity

or by instantiating a component called lpm_latch from the

Library of Parameterized Modules (LPM).

14. An LPM component is a standard component with certain

properties, called parameters, that can be specified when the

component is instantiated. The inputs and outputs of an LPM

component are called ports. Parameter values are assigned in

the generic map of a component instantiation statement.

Component port names are associated with user port names

in the port map of a component instantiation statement.

15. A flip-flop is like a gated latch that responds to the edge of a

pulse applied to an enable input called CLOCK. A flip-flop

output will change only when the input makes a transition

from LOW to HIGH (for a positive edge-triggered device) or

HIGH to LOW (for a negative edge-triggered device).

16. In a positive edge-triggered D flip-flop, Q follows D when

there is a positive edge on the clock input.

17. D flip-flops are used primarily for data storage and transfer.

18. A JK flip-flop has two synchronous inputs, called J and K. J

acts as an active-HIGH set input. K acts as an active-HIGH

reset function. When both inputs are asserted, the flip-flop

toggles between 0 and 1 with each applied clock pulse.

19. The toggle function in a JK flip-flop is implemented with additional

cross-coupled feedback from the latch gate outputs

to the steering gate inputs.

20. A chain of JK flip-flops can implement an asynchronous binary

counter if the Q of each flip-flop is connected to the

❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚

0 0 Qt Q_t No change

0 1 0 1 Reset

1 0 1 0 Set

1 1 0 0 Forbidden

7. A NAND latch has active-LOW inputs and is described by

the following function table:

S_ R_ Qt_1 Q_t_1 Function

0 0 1 1 Forbidden

0 1 1 0 Set

1 0 0 1 Reset

1 1 Qt Q_t No change

8. A NAND latch can be used as a switch debouncer for a

switch with a grounded common terminal, a normally open,

and a normally closed contact. When the switch operates,

one contact closes, resetting the latch on the first bounce.

Further bounces are ignored. When the switch returns to its

normal position, it sets the latch on the first bounce and further

bounces are ignored.

clock input of the next. Although this is an easy way to

create a counter, it is seldom used because internal flip-flop

delays result in unwanted intermediate states in the count

sequence.

21. JK flip-flops can be combined with a network of logic gates

to make a synchronous binary counter. The gates are connected

in such a way that each flip-flop toggles when all previous

bits are HIGH; otherwise the flip-flops are in a no

change state. Although more complex than an asynchronous

counter, a synchronous counter is free of unwanted intermediate

states.

and clear (reset) functions. Since these functions are connected

directly to the latch gates of a flip-flop, they act immediately,

without waiting for the clock. In most cases, these

functions are active-LOW.

23. Asynchronous inputs, such as preset and clear, are usually

designed so that they will override the synchronous inputs,

such as D or JK.

24. Unused asynchronous inputs should be disabled by tying

them to a logic HIGH (for an active-LOW input). Flip-flop

primitives in MAX_PLUS II automatically have their asynchronous

inputs connected to HIGH unless otherwise specified

by a design entry file.

25. The outputs of a T (toggle) flip-flop toggle with each clock

pulse when the T input is HIGH and do not change when T is

LOW.

setup and hold time, propagation delay, minimum pulse

width, and recovery time.

27. Setup time is the time before a clock edge that a synchronous

input must be held steady. Hold time is the time after an applied

clock edge that an input level must be held constant.

28. Propagation delay is the time for an input change, such as on

CLK or C_L_R_, to have an effect on an output, such as Q. Propagation

time is always indicated with respect to the change in

output level: tpLH for a LOW-to-HIGH output transition and

tpHL for a HIGH-to-LOW output change.

29. Minimum pulse width, tw, indicates how long a CLK or C_L_R_

input must be held after an active edge or level is applied before

returning to the original level.

30. Recovery time is the minimum time required from the end of

an active level on one input (such as C_L_R_) to an active CLK

edge.

G L O S S A R Y

flip-flop’s Q outputs immediately, without waiting for a pulse at

the CLK input. Examples include preset and clear inputs.

Clear An asynchronous reset function.

CLOCK An enabling input to a sequential circuit that is sensitive

to the positive- or negative-going edge of a waveform.

(positive edge) transition of a pulse waveform.

the active edge of a CLOCK input to an active-level pulse

at the internal latch’s SET and RESET inputs.

Edge-sensitive Edge-triggered.

Edge-triggered Enabled by the positive or negative edge of a

digital waveform.

changes when its CLOCK input receives either an edge or a

pulse, depending on the device.

Gated SR latch An SR latch whose ability to change states is

controlled by an extra input called the ENABLE input.

of a component to a value for that instance of the component.

flip-flop must remain stable after the active CLK transition is

finished.

Latch A sequential circuit with two inputs called SET and RESET,

which make the latch store a logic 0 (reset) or 1 (set) until

actively changed.

Level-sensitive Enabled by a logic HIGH or LOW level.

Library of Parameterized Modules (LPM) A standardized

set of components for which certain properties can be specified

when the component is instantiated.

Master Reset An asynchronous reset input used to set a sequential

circuit to a known initial state.

that can be specified when the component is instantiated.

component to the name of a port, variable, or signal in a design

entity that uses the component.

Propagation delay The time required for the output of a digital

circuit to change states after a change at one or more of its inputs.

pulse applied to a CLK, C_L_R_, or P_R_E_ input, as measured from

the midpoint of the leading edge of the pulse to the midpoint of

the trailing edge.

trailing edge of a C_L_R_ or P_R_E_ pulse to the midpoint of an active

that makes the latch store a logic 0.

only on the present combination of inputs, but also on the history

of the circuit.

Set 1. The stored HIGH state of a latch circuit. 2. A latch input

that makes the latch store a logic 1.

of a flip-flop to be stable before a CLK pulse is applied.

Problems 317

Steering gates Logic gates, controlled by the ENABLE input

of a gated latch, that steer a SET or RESET pulse to the correct

input of an SR latch circuit.

Synchronous Synchronized to the system clock.

Synchronous inputs The inputs of a flip-flop that do not affect

the flip-flop’s Q outputs unless a clock pulse is applied. Examples

include D, J, and K inputs.

Toggle Alternate between binary states with each applied

clock pulse.

HIGH and LOW states on each applied clock pulse when a synchronous

input, called T, is active.

Transparent latch (gated D latch) A latch whose output follows

its data input when its ENABLE input is active.

P R O B L E M S

Section 7.1 Latches

7.1 Complete the timing diagram in Figure 7.66 for the active-

HIGH latch shown. The latch is initially set.

7.67.

Problem 7.2

Timing Diagram

FIGURE 7.66

Problem 7.1

Timing Diagram

FIGURE 7.68

Problem 7.3

Timing Diagram

7.3 Complete the timing diagram in Figure 7.68 for the active-

LOW latch shown.

motor starter. The motor runs when Q _ 1 and stops

when Q _ 0. (Problem continues . . .)

FIGURE 7.69

Problem 7.4

Latch for Motor Starter

318 C H A P T E R 7 • Introduction to Sequential Logic

The motor is housed in a safety enclosure that has an

access hatch for service. A safety interlock prevents the

motor from running when the hatch is open. The HATCH

switch opens when the hatch opens, supplying a logic

HIGH to the circuit. The START switch is a normally

open momentary-contact pushbutton (LOW when

pressed). The STOP switch is a normally closed momentary-

contact pushbutton (HIGH when pressed).

Draw the timing diagram of the circuit, showing START,

events:

Briefly describe the functions of the three switches and

how they affect the motor operation.

Section 7.2 NAND/NOR Latches

7.5 Draw a NAND latch, correctly labeling the inputs and

outputs. Describe the operation of a NAND latch for all

four possible combinations of S_ and R_.

7.6 Draw a NOR latch, correctly labeling the inputs and outputs.

Describe the operation of a NOR latch for all four

possible combinations of S and R.

7.7 The timing diagram in Figure 7.70 shows the input waveforms

of a NAND latch. Complete the diagram by showing

the output waveforms.

7.8 Figure 7.71 shows the input waveforms to a NOR latch.

Draw the corresponding output waveforms.

circuit.

latch.

latch.

forbidden state at some point. Even under this condition, it

is still possible to produce unambiguous output waveforms.

Refer to Figures 7.18 and 7.19 for guidance.)

each of the following sequences of events:

i. S_ and R_ are both LOW; S_ goes HIGH before R_.

ii. S_ and R_ are both LOW; R_ goes HIGH before S_.

iii. S_ and R_ are both LOW; S_ and R_ go HIGH simultaneously.

b. State why S_ _ R_ _ 0 is a forbidden state for the

NAND latch.

above transitions.

of the following sequences of events:

i. S and R are both HIGH; S goes LOW before R.

ii. S and R are both HIGH, R goes LOW before S.

iii. S and R are both HIGH, S and R go LOW simultaneously.

FIGURE 7.70

Problem 7.7

Timing Diagram

FIGURE 7.71

Problem 7.8

Input Waveforms to a NOR

Latch

Problem 7.9

Input Waveforms to a Latch

Problems 319

transitions listed in part a of this question.

latch.

switching waveforms of a single-pole double-throw

(SPDT) switch.

a. Briefly explain how this effect arises.

b. Draw a NAND latch circuit that can be used to eliminate

this mechanical bounce, and briefly explain how

it does so.

Section 7.3 Gated Latches

7.13 Complete the timing diagram for the gated latch shown in

Figure 7.74.

Figure 7.75.

Problem 7.12

Effect of Mechanical Bounce on

a SPDT Switch

Problem 7.13

Gated Latch

FIGURE 7.75

Problem 7.14

Gated Latch

320 C H A P T E R 7 • Introduction to Sequential Logic

7.15 A pump motor can be started at two different locations

with momentary-contact pushbuttons S1 and S2. It can be

stopped by momentary-contact pushbuttons ST1 and ST2.

As in Problem 7.4, a RUN input on the motor controller

must be kept HIGH to keep the motor running. After the

motor is stopped, a timer prevents the motor from starting

for 5 minutes.

Draw a circuit block diagram showing how an SR

latch and some additional gating logic can be used in

such an application. The timer can be shown as a block

activated by the STOP function. Assume that the timer

output goes HIGH for 5 minutes when activated.

different gated latches. The ENABLE waveforms for the

latches are shown as EN1 and EN2. Draw the output

waveforms Q1 and Q2, assuming that S, R, and EN are all

active HIGH. Which output is least prone to synchronization

errors? Why?

Problem 7.16

Waveforms

FIGURE 7.77

Problem 7.17

Waveforms

Problems 321

of a 4-bit transparent latch. Complete the timing diagram

by drawing the waveforms for Q1 to Q4.

7.18 An electronic direction finder aboard an aircraft uses a 4-

bit number to distinguish 16 different compass points as

follows:

Direction Degrees Gray Code

N 0/360 0000

NNE 22.5 0001

NE 45 0011

ENE 67.5 0010

E 90 0110

ESE 112.5 0111

SE 135 0101

SSE 157.5 0100

S 180 1100

SSW 202.5 1101

SW 225 1111

WSW 247.5 1110

W 270 1010

WNW 295.5 1011

NW 315 1001

NNW 337.5 1000

The output of the direction finder is stored in a 4-bit

latch so that the aircraft flight path can be logged by a

computer. The latch is periodically updated by a continuous

pulse on the latch enable line.

Figure 7.78 shows a sample reading of the direction

finder’s output as presented to the latch. (Problem continues

. . .)

Q1

D1

Q3

Q4

Q1

D3

D2

D1

4-bit Latch NNE NE ENE E ESE SE SSE S SSW SW WSW W WNW NW NNW N

Compass Data

converter

D2

Q3

Q4

D4