Chapter 1 Basic Principles of Digital Systems outlin e 1


FIGURE 7.78 Problem 7.18 Direction Finder and Sample Output 322 C H A P T E R 7 •



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FIGURE 7.78

Problem 7.18

Direction Finder and Sample Output



322 C H A P T E R 7 • Introduction to Sequential Logic

a. Complete the timing diagram by filling in the data for

the Q outputs.



b. Based on the completed timing diagram of Figure

7.78, make a rough sketch of the aircraft’s flight path

for the monitored time.

7.19 Write a VHDL file for an 8-bit latch, using LATCH primitives.

Create a simulation file that demonstrates the operation

of all eight bits.

7.20 Write a VHDL file for an 8-bit latch, using a component

from the Library of Parameterized Modules. Create a

simulation file that tests the latch for all eight bits.

Section 7.4 Edge-Triggered D Flip-Flops

7.21 The waveforms in Figure 7.79 are applied to the inputs of

a positive edge-triggered D flip-flop and a gated D latch.

Complete the timing diagram where Q1 is the output of

the flip-flop and Q2 is the output of the gated latch. Account

for any differences between the Q1 and Q2 waveforms.

7.22 Complete the timing diagram for a positive edge-triggered

D flip-flop if the waveforms shown in Figure 7.80

are applied to the flip-flop inputs.

7.23 Repeat Problem 7.22 for the waveforms shown in Figure

7.81.


7.24 Repeat Problem 7.22 for the waveforms shown in Figure

7.82.


7.25 Draw a logic diagram of a D flip-flop configured for toggle

mode. (Hint: The D input must always be the opposite

of the Q output.)

7.26 Write a VHDL file that defines a 12-bit D flip-flop with a

clock common to all flip-flops, using MAX_PLUS II

primitives. The component declaration for the DFF component

is as follows:



FIGURE 7.79

Problem 7.21

Waveforms

FIGURE 7.80

Problem 7.22

Waveforms

FIGURE 7.81

Problem 7.23

Waveforms

Problems 323

COMPONENT DFF

PORT (d : IN STD_LOGIC;

clk : IN STD_LOGIC;

clrn : IN STD_LOGIC;

prn : IN STD_LOGIC;

q : OUT STD_LOGIC;

END COMPONENT;

Disregard the clrn (active-LOW clear) and prn (active-

LOW preset) ports for this problem. (Hint: you may

have to use a component declaration in your file that only

declares the ports d, clk, and q.)

7.27 Write a VHDL file that creates a 12-bit D flip-flop, using

the LPM component lpm_ff. (This component is instantiated

as a D flip-flop by default. The required LPM component

port names are: data, clock, and q.)



Section 7.5 Edge-Triggered JK Flip-Flops

7.28 The waveforms in Figure 7.83 are applied to a negative

edge-triggered JK flip-flop. Complete the timing diagram

by drawing the Q waveform.

7.29 Repeat Problem 7.28 for the waveforms in Figure 7.84.

7.30 Given the inputs x, y, and z to the circuit in Figure 7.85,

draw the waveform for output Q.



FIGURE 7.82

Problem 7.24

Waveforms

CLK


J

K

Q



FIGURE 7.83

Problem 7.28

Waveforms

CLK


J

K

Q



FIGURE 7.84

Problem 7.29

Waveforms

CLK


CLK CLK

xy

z



x

J

K



y

z

Q



Q

Q

FIGURE 7.85

Problem 7.30

Inputs to Circuit



324 C H A P T E R 7 • Introduction to Sequential Logic

7.31 Assume that all flip-flops in Figure 7.86 are initially set.

Draw a timing diagram showing the CLK, Q0, Q1, and Q2

waveforms when eight clock pulses are applied. Make a

table showing each combination of Q2, Q1, and Q0. What

pattern do the outputs form over the period shown on the

timing diagram?



7.32 Refer to the JK flip-flop circuit in Figure 7.87. Is the circuit

synchronous or asynchronous? Explain your answer.



7.33 Assume all flip-flops in the circuit in Figure 7.87 are

reset. Analyze the operation of the circuit when sixteen

clock pulses are applied by making a table showing

the sequence of states of Q3Q2Q1Q0, beginning at

0000.

7.34 Draw a timing diagram showing the sequence of states

from the table derived in Problem 7.33.



7.35 The waveforms shown in Figure 7.88 are applied to a

negative edge-triggered JK flip-flop. The flip-flop’s Preset

and Clear inputs are active LOW. Complete the timing diagram

by drawing the output waveforms.



FIGURE 7.86

Problem 7.31

Flip-Flops

Q

JKFF



J

K

CLRN



PRN

CLK INPUT

Q

JKFF


J

CLRN


PRN

Q

JKFF



AND2

CLRN


PRN

OUTPUT


OUTPUT

OUTPUT q0

q1

q2

K K



J

AND3


VCC

Q

JKFF



CLRN

PRN


K

J

OUTPUT q3



FIGURE 7.87

Problem 7.32

Flip-Flop Circuit

FIGURE 7.88

Problem 7.35

Waveforms

CLK


J

K

PRE



CLR

Q

Q



Problems 325

7.36 Repeat Problem 7.35 for the waveforms in Figure 7.89.

7.37 Create a MAX_PLUS II Graphic Design File for the

synchronous circuit in Figure 7.87. Modify the circuit to

add an asynchronous Master Reset function. Create a

simulation file to verify the circuit operation.



7.38 Modify the gdf created in Problem 7.37 to include a Master

Reset function and an asynchronous preset function that will

set the state of the circuit to Q3Q2Q1Q0 _ 1010 when activated.

Create a simulation file to verify the circuit operation.



7.39 The term asynchronous is sometimes used to refer to the

configuration of a circuit (e.g., a 3-bit asynchronous

counter) and sometimes to a type of input to a device

(e.g., an asynchronous clear input). Briefly explain how

these two usages are similar and how they are different.

7.40 Write a VHDL file for a 12-bit D flip-flop that uses

MAX_PLUS II DFF primitives, similar to that in Problem

7.26. Include active-LOW asynchronous clear (CLRN)

and preset (PRN) inputs. Create a simulation file to verify

the operation of your design.

7.41 Write aVHDL file for a 12-bit D flip-flop with asynchronous

preset and clear, using the LPM component lpm_ff,

similar to that in Problem 7.27. Required ports: data,

clock, aclr (asynchronous clear), aset (asynchronous set),

and q. Ports aset and aclr are active-HIGH. Add two signals

to theVHDL design to make them active-LOW. Create

a simulation file to verify the operation of your design.



Section 7.6 Edge-Triggered T Flip-Flops

7.42 The T and CLK waveforms for a positive-edge triggered

T flip-flop is shown in Figure 7.90. Complete the timing

diagram.

7.43 The T and CLK waveforms for a positive-edge triggered

T flip-flop is shown in Figure 7.91. Complete the timing

diagram.

CLK


J

K

PRE



CLR

Q

FIGURE 7.89

Problem 7.36

Waveforms



FIGURE 7.90

Problem 7.42

Timing Diagram

T

CLK



Q

T

CLK



Q

FIGURE 7.91

Problem 7.43

Timing Diagram

326 C H A P T E R 7 • Introduction to Sequential Logic

FIGURE 7.93

Problem 7.50

Timing Diagram

FIGURE 7.92

Problem 7.49

Timing Parameters

A N S W E R S T O S E C T I O N R E V I E W P R O B L E M S



Section 7.1

7.1 The latch resets (i.e., Q goes LOW) upon receiving the first

reset pulse. At that point, the latch is already reset, so further

pulses are ignored.



Section 7.2

7.2 The NOR latch has active-HIGH inputs. If you make both

inputs HIGH, you are attempting to set and reset the latch at the

same time, which is a contradictory action. A NAND latch has

active-LOW inputs. Therefore, if both inputs are HIGH, neither

the set nor reset function activates and there is no change on the

latch output.

Section 7.3

7.3


LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

LIBRARY altera;

USE altera.maxplus2.ALL;

ENTITY lch16prm IS

PORT(d_in : IN STD_LOGIC_VECTOR (15 downto 0);

enable : IN STD_LOGIC;

q_out : OUT STD_LOGIC_VECTOR (15 downto 0) );

END lchl6prm;

ARCHITECTURE a OF lch16prm IS

BEGIN

—— Instantiate a latch from a MAX_PLUS II primitive



latch4:

FOR i IN 15 downto 0 GENERATE

latch_primitive: latch

PORT MAP (d __ d in (i),

ena __ enable, q __ q out (i) );

END GENERATE;

END a;

Section 7.4

7.4 The edge detector circuit in the clock circuit accounts for

the operational difference between a D flip-flop and a D latch. It

works by using the difference in internal delay times between

the gates that comprise the flip-flop’s clock input circuit.

Section 7.5

7.5 The flip-flops in asynchronous circuits are not all clocked at

the same time; they are asynchronous with respect to the system

clock. The flip-flops in a synchronous circuit have a common

clock connection, which makes them synchronous to the system

clock. The disadvantage to asynchronous circuits is that the internal

delays of flip-flops can lead to unwanted intermediate

states, since the flip-flops do not all change at the same time.



7.44 Refer to the synchronous circuit in Figure 7.87. Create a

MAX_PLUS II Graphic Design File for a circuit with

the same function, using T flip-flops rather than JK flipflops.

Include an asynchronous reset input in the circuit.

Create a simulation file to test the operation of the circuit.

7.45 Write a VHDL file that implements the circuit you

drew in Problem 7.44. Use TFF primitives in the

design.

Section 7.7 Timing Parameters

7.46 Use a TTL or high-speed CMOS data sheet, as appropriate,

to look up the setup and hold times of the following

devices:

a. 74LS74A

b. 74HC76

c. 74LS76A

d. 74LS107A

e. 74ALS112A

f. 74HC112

7.47 Draw a timing diagram showing the setup and hold times

for a 74LS76A flip-flop.



7.48 Draw timing diagrams (to scale) showing setup and hold

times, minimum CLK and C_L_R_ pulse widths, recovery

time, and propagation delay times from CLK and C_L_R_ for

both 74LS107A and 74HC107 flip-flops.



7.49 Write names and values of the JK flip-flop timing parameters

illustrated in Figure 7.92.



7.50 Repeat Problem 7.49 for the timing diagram in

Figure 7.93.

Answers to Review Section 327

Section 7.6

7.6 The circuit is shown in Figure 7.94.



Section 7.7

7.7 The parameter is called propagation delay. For the specified

output transition, the symbol is tpHL.

Q

TFF



T

CLRN


PRN

CLK INPUT

Q

TFF


T

CLRN


PRN

Q

TFF



AND2

CLRN


PRN

OUTPUT


OUTPUT

OUTPUT Q0

Q1

Q2

T



VCC

FIGURE 7.94

Solution to Section Review Problem 7.6


329

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❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚

C H A P T E R 8

Introduction to Programmable

Logic Architectures

O U T L I N E



8.1 Programmable

Sum-of-Products

Arrays

8.2 PAL Fuse Matrix and

Combinational

Outputs

8.3 PAL Outputs with

Programmable

Polarity

8.4 PAL Devices with

Programmable

Polarity

8.5 Universal PAL and

Generic Array Logic



8.6 MAX7000S CPLD

8.7 FLEX10K CPLD

C H A P T E R O B J E C T I V E S

Upon successful completion of this chapter, you will be able to:

• Draw a diagram showing the basic hardware conventions for a sum-ofproducts-

type programmable logic device.

• Describe the structure of a programmable array logic (PAL) AND matrix.

• Draw fuses on the logic diagram of a PAL to implement simple logic

functions.

• Describe the structures of combinational, programmable polarity, and

registered PAL outputs.

• Determine the number and type of outputs from a PAL/GAL part number.

• Explain the structure of an output logic macrocell (OLMC).

• State differences between Universal PAL and generic array logic (GAL)

and standard PAL.

• Interpret the logic diagrams of Universal PAL and GAL devices to determine

the number of outputs and product terms and the type of control

signals available in a device.

• Interpret block diagrams to determine the basic structure of an Altera

MAX7000S CPLD, including macrocell configuration, Logic Array Blocks

(LABs), control signals, and product term expanders.

• State the differences between PLDs based on sum-of-products (SOP) architecture

versus look-up table (LUT) architecture.

• Interpret block diagrams to determine the basic structure of a logic element

in an Altera FLEX10K CPLD, including look-up tables, cascade chains,

carry chains, and control signals.

• Interpret block diagrams to determine how a logic element in a FLEX10K

device relates to the overall structure of the device.

• Interpret block diagrams to determine how logic array blocks and embedded

array blocks relate to the overall structure of a FLEX10K CPLD.

In the past several chapters, we have been using Altera’sMAX_PLUS II software to make

circuit designs for downloading into a complex programmable logic device (CPLD).We

have treated this device as a black box—something whose function we design, but whose

structure we do not really understand. In this chapter, we will look inside the box. _

330 C H A P T E R 8 • Introduction to Programmable Logic Architectures

Before we examine the structure of an Altera MAX7000S CPLD, we will look at the

internal structure of several simpler devices that are based on similar technologies, such as

the PAL16L8 and PAL16R8 low-density PLDs (largely for an historical overview), the

PALCE16V8, and the GAL22V10.

These devices are based on programmable matrices of sum-of-products (SOP)

circuits, as is the Altera MAX series of devices. The main programming element is the

EEPROM (electrically erasable programmable read-only memory) cell. EEPROM-based

devices will retain their programmed data when power is removed from the device.

The Altera FLEX series of CPLDs is based on another technology altogether. It stores

logic functions in look-up tables (LUTs) that act as truth tables with four input bits. The

main logic element of the FLEX series is the SRAM (static random access memory) cell.

SRAM-based CPLDs must have their programming data loaded every time they are

powered up. They have the advantage of being faster than EEPROM devices, with a higher

bit capacity.

8.1 Programmable Sum-of-Products Arrays



Product line A single line on a logic diagram used to represent all inputs to an

AND gate (i.e., one product term) in a PLD sum-of-products array.



Input line A line that applies the true or complement form of an input variable to

the AND matrix of a PLD.



PAL Programmable array logic. Programmable logic with a fixed OR matrix and

a programmable AND matrix.

The original programmable logic devices (PLDs) consisted of a number of AND and

OR gates organized in sum-of-products (SOP) arrays in which connections were made or

broken by a matrix of fuse links. An intact fuse allowed a connection to be made; a blown

fuse would break a connection.

Figure 8.1a shows a simple fuse matrix connected to a 4-input AND gate. True and

complement forms of two variables, A and B, can be connected to theAND gate in any combination

by blowing selected fuses. In Figure 8.1a, fuses for A_ and B are blown. The output

of theAND gate represents the product term AB_, the logical product of the intact fuse lines.

Figure 8.1b shows a more compact notation for the AND-gate fuse matrix. Rather than

showing each AND input individually, a single line, called the product line, goes into the

AND gate, crossing the true and complement input lines. An intact connection

to an input line is shownby an “X” on the junction between the input line and the product line.

A symbol convention similar to Figure 8.1b has been developed for programmable

logic. Figure 8.2 shows an example.

The circuit shown in Figure 8.2 is a sum-of-products network whose Boolean

expression is given by:



F _ A_ B_ C _ A B_ C_

The product terms are accumulated by the AND gates as in Figure 8.1b. A buffer having

true and complement outputs applies each input variable to the AND matrix, thus

producing two input lines. Each product line can be joined to any input line by leaving the

corresponding fuse intact at the junction between the input and product lines.

If a product line, such as for the third AND gate, has all its fuses intact, we do not show

the fuses on that product line. Instead, this condition is indicated by an “X” through the

gate. The output of the third AND gate is a logic 0, since (A_ A B_ B C_ C) _ 0. This is necessary

to enable the OR gate output:

A_ B_ C _ A B_ C_ _ 0 _ A_ B_ C _ A B_ C_

K E Y T E R M S



8.1 • Programmable Sum-of-Products Arrays 331

Unconnected inputs are HIGH (e.g., A_ _ 1 _ B_ _ 1 _ 1 _C _ A_ B_ Cfor the the first product

line).

If the unused AND output was HIGH, the function F would be:



A_ B_ C + A B_ C_ + 1 = 1

The configuration in Figure 8.2, with a programmable AND matrix and a hardwired

OR connection, is called PAL (programmable array logic) architecture.1

Since any combinational logic function can be written in SOP form, any Boolean

function can be programmed into these PLDs by blowing selected fuses. The programming

A B


A B

A B


A B

A B


A B

a. Crosspoint fuse matrix ( A and B intact )

b. PLD notation for fuse matrix

Blown


Intact

FIGURE 8.1

Crosspoint Fuse Matrix



FIGURE 8.2

PLD Symbology

1PAL is a registered trademark of Vantis Semiconductor.

332 C H A P T E R 8 • Introduction to Programmable Logic Architectures

is done by special equipment and its associated software. The hardware and software selects

each fuse individually and applies a momentary high-current pulse if the fuse is to be

blown.


The main problem with fuse-programmable PLDs is that they can be programmed

one time only; if there is a mistake in the design and/or programming or if the design

is updated, we must program a new PLD. More recent technology has produced several

types of erasable PLDs, based not on fuses but on floating-gate metal-oxidesemiconductor

transistors. These transistors also form the basis of memory technologies

such as electrically erasable programmable read-only memory (EEPROM or

E2PROM).

8.2 PAL Fuse Matrix and Combinational Outputs

JEDEC Joint Electron Device Engineering Council

JEDEC file An industry-standard form of text file indicating which fuses are

blown and which are intact in a programmable logic device.



Text file An ASCII-coded document stored on disk.

Checksum An error-checking code derived from the accumulated sum of the data

being checked.



Cell A programmable location in a PLD, specified by the intersection of an input

line and a product line.



Product line first cell number The lowest cell number on a particular product

line in a PAL AND matrix where all cells are consecutively numbered.



Input line number A number assigned to a true or complement input line in a

PAL AND matrix.



Multiplexer A circuit that selects one of several signals to be directed to a

single output.

Figure 8.3 shows the logic diagram of a PAL16L8 PAL circuit. This device can produce up

to eight different sum-of-products expressions, one for each group of AND and OR gates.

The device has active-LOW tristate outputs, as indicated by the “L” in the part number.

Each is controlled by a product line from the related AND matrix.

The pins that can be used only as inputs or outputs are marked “I” or “O,” respectively.

Six of the pins can be used as inputs or outputs and are marked “I/O.” The

I/O pins can also feed back a derived Boolean expression into the matrix, where it

can be employed as part of another function. A detail of an I/O section is shown in

Figure 8.4.

The part number of a PAL device gives the designer information about the number of

inputs and outputs and their configurations, as follows:

Number of inputs

Output type:

H _ Active HIGH

L _ Active LOW

P _ Programmable polarity

R _ Registered (D flip-flop)

X _ XOR registered

C _ Complementary (both HIGH and LOW)

Number of (registered) outputs

PAL 16 R 8

K E Y T E R M S




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