Table 7.7 Function Tables for Edge-Triggered JK Flip-Flops CLK J K Q

↑0 0 Qt Q_t No change ↓0 0 Qt Q_t No change

↑0 1 0 1 Reset ↓0 1 0 1 Reset

↑1 0 1 0 Set ↓1 0 1 0 Set

↑1 1 Q_t Qt Toggle ↓1 1 Q_t Qt Toggle

0 X X Qt Q_t Inhibited 0 X X Qt Q_t Inhibited

1 X X Qt Q_t Inhibited 1 X X Qt Q_t Inhibited

↓X X Qt Q_t Inhibited ↑X X Qt Q_t Inhibited

Positive Edge-Triggered Negative Edge-Triggered

FIGURE 7.45

Edge-Triggered JK Flip-Flops

JK Flip-Flop Circuit (Simplified)

❘❙❚ EXAMPLE 7.8 The J, K, and CLK inputs of a negative edge-triggered JK flip-flop are as shown in the timing

diagram in Figure 7.48. Complete the timing diagram by drawing the waveforms for Q

and Q_. Indicate which function (no change, set, reset, or toggle) is performed at each clock

pulse. The flip-flop is initially reset.

FIGURE 7.47

Toggle Action of a JK Flip-Flop

Example 7.8

Timing Diagram (Negative-Edge-Triggered JK Flip-Flop)

SOLUTION The completed timing diagram is shown in Figure 7.48. The outputs change

only on the negative edges of the CLK waveform. Note that the same output sometimes results

from different inputs. For example, the function at clock pulse 4 is reset and the function

at pulses 5 and 6 is no change, but the Q waveform is LOW in each case.

❘❙❚ EXAMPLE 7.9 The toggle function of a JK flip-flop is often used to generate a desired output sequence

from a series of flip-flops. The circuit shown in Figure 7.49 is configured so that all flipflops

are permanently in toggle mode.

Assume that all flip-flops are initially reset. Draw a timing diagram showing the CLK,

combination of Q2, Q1, and Q0. What pattern do the outputs form over the period shown on

the timing diagram?

SOLUTION The circuit timing diagram is shown in Figure 7.50. All flip-flops are in toggle

mode. Each time a negative clock edge is applied to the flip-flop CLK input, the Q output

will change to the opposite state.

FIGURE 7.49

Example 7.9

Circuit

FIGURE 7.50

Example 7.9

Timing Diagram

For flip-flop 0, this happens with every clock pulse, since it is clocked directly by the

CLK waveform. Each of the other flip-flops is clocked by the Q output waveform of the

previous stage. Flip-flop 1 is clocked by the negative edge of the Q0 waveform. Flip-flop 2

toggles when Q1 goes from HIGH to LOW.

Table 7.8 shows the flip-flop outputs after each clock pulse. The outputs form a 3-bit

number that counts from 000 to 111 in binary sequence, then returns to 000 and repeats.

This flip-flop circuit is called a 3-bit asynchronous counter. ❘❙❚

Synchronous versus Asynchronous Circuits

Synchronous Synchronized to the system clock.

Asynchronous Not synchronized to the system clock

The asynchronous counter in Figure 7.49 has the advantage of being simple to construct

and analyze. However, because it is asynchronous (that is, not synchronized to a single

clock), it is seldom used in modern digital designs. The main problem with this and other

asynchronous circuits is that their outputs do not change at the same time, due to delays

in the flip-flops. This yields intermediate states that are not part of the desired output

sequence.

K E Y T E R M S

Outputs for Circuit in Figure

7.49

Clock

Pulse Q2 Q1 Q0

0 0 0 0

2 0 1 0

4 1 0 0

6 1 1 0

8 0 0 0

Figure 7.51 shows a simulation of a circuit similar to that in Figure 7.49. The outputs

are shown separately, and also as a group labeled Q[2..0] that shows the combined binary

value of the outputs.

➥ asynch3.gdf

asynch3.scf

FIGURE 7.51

Simulation of a 3-bit Asynchronous Counter

Figure 7.52 shows a detail of the simulation at the point where the output goes from

7 to 0 (111 to 000). At 300 ns, the circuit output is 111. A negative clock edge, applied to

flip-flop 0, makes Q0 toggle after a short delay. The output is now 110 (_610). The resulting

negative edge on Q0 clocks flip-flop 1, making it toggle, and yields a new output of 100

(_410). The negative edge on Q1 clocks flip-flop 2, making the output equal to 000 after a

short delay.

Detail of simulation for a 3-bit

Asynchronous Counter

Thus, the output goes through two short intermediate states that are not in the desired

output sequence. Instead of going directly from 111 to 000, as in Figure 7.50, the output

goes in the sequence 111–110–100–000. We see in Figure 7.51 that the counter output goes

through one or more intermediate transitions after each negative edge of the Q0 waveform.

In other words, intermediate states arise whenever a change propagates through more than

one flip-flop. This happens because the flip-flops are clocked from different sources.

➥ sync3.gdf

JKFF

K

CLRN

CLK INPUT

Q

JKFF

CLRN

Q

AND2 JKFF

PRN

OUTPUT

Q1

Q2

J

VCC

3-bit Synchronous Counter

Figure 7.53 shows the circuit of a 3-bit synchronous counter. Unlike the circuit in

Figure 7.49, the flip-flops in this circuit are clocked from a common source. Therefore,

flip-flop delays do not add up through the circuit, and all the outputs change at the same

time. Figure 7.54 shows a simulation of the circuit of Figure 7.53. Note that the outputs

progress in a binary sequence, and there are no intermediate states.

Simulation of a 3-bit Synchronous Counter

The circuit works as follows:

1. Flip-flop 0 is configured for toggle mode (J0K0 _ 11). Since the flip-flops in Figure

7.53 are positive edge-triggered, Q0 toggles on each positive clock edge.

2. Q0 is connected to inputs J1 and K1. Since these inputs are tied together, only two states

are possible: no change (JK_00) or toggle (JK_11). If Q0_1, Q1 toggles. Otherwise,

it does not change. This results in a Q1 waveform that toggles at half the rate of Q0.

3. J2 and K2 are both tied to the output of an AND gate. The AND gate output is HIGH if

both Q1 and Q0 are HIGH. This makes Q2 toggle, since J2K2 _ 11. In all other cases,

there is no change on Q2. The result of this is that Q2 toggles every fourth clock pulse,

the only times when Q1 and Q0 are both HIGH.

Asynchronous Inputs (Preset and Clear)

outputs unless a clock pulse is applied. Examples include D, J, and K inputs.

immediately, without waiting for a pulse at the CLK input. Examples include

preset and clear inputs.

Preset An asynchronous set function.

Clear An asynchronous reset function.

The D, J, and K inputs of the flip-flops examined so far are called synchronous inputs.

This is because any effect they have on the flip-flop outputs is synchronized to the CLK

input.

two functions usually provided are preset, an asynchronous set function, and clear, an

asynchronous reset function. These functions are generally active LOW, and are abbreviated

P_R_E_ and C_L_R_.

Figure 7.55 shows a modification to the JK flip-flop of Figure 7.46. The P_R_E_ and C_L_R_

inputs have direct access to the latch gates of the flip-flop and thus are not affected by the

K E Y T E R M S

override any synchronous input functions currently active.

❘❙❚ EXAMPLE 7.10 The waveforms for the CLK, J, K, P_R_E_, and C_L_R_ inputs of a negative edge-triggered JK

flip-flop are shown in the timing diagram of Figure 7.56. Complete the diagram by drawing

the waveform for output Q.

FIGURE 7.55

P_R_E_ and C_L_R_ Inputs

Example 7.10

Waveforms

SOLUTION The Q waveform is shown in Figure 7.56. The asynchronous inputs cause an

immediate change in Q, whereas the synchronous inputs must wait for the next negative

clock edge. If asynchronous and synchronous inputs are simultaneously active, the asynchronous

inputs have priority. This occurs in two places: pulse 3 (K, P_R_E_) and pulse 10

The diagram shows the synchronous functions (no change, reset, set, and toggle) at each

clock pulse and the asynchronous functions (preset and clear) at the corresponding transition

points.

The function table of a negative edge-triggered JK flip-flop with preset and clear functions

is shown in Table 7.9.

7.5 • Edge-Triggered JK Flip-Flops 309

If preset and clear functions are not used, they should be disabled by connecting

them to logic HIGH (for active-LOW inputs). This prevents them from being activated

inadvertently by circuit noise. The synchronous functions of some flip-flops

will not operate properly unless P_R_E_ and C_L_R_ are HIGH. In MAX_PLUS II, the

asynchronous inputs of all flip-flop primitives are set to a default level of HIGH.

known initial state.

Figure 7.57 shows an application of asynchronous clear inputs in a 3-bit synchronous

counter. An input called RESET is tied to the asynchronous C_L_R_ inputs of all flipflops.

The counter output is set to 000 when the RESET line goes LOW.

K E Y T E R M

N O T E

Table 7.9 Function Table of a Negative Edge-Triggered JK Flip-Flop with Preset and Clear

Functions

1 1 ↓0 1 0 1 Reset

1 1 ↓1 0 1 0 Set

1 1 ↓1 1 Q_t Qt Toggle

1 0 X X X 0 1 Clear

0 0 X X X 1 1 Forbidden

1 1 0 X X Qt Q_t Inhibited

1 1 1 X X Qt Q_t Inhibited

1 1 ↑X X Qt Q_t Inhibited

X _ Don’t care ↓_ HIGH-to-LOW transition

Qt _ Present state of Q ↑_ LOW-to-HIGH transition

Qt_1 _ Next state of Q

Q

JKFF

K

CLRN

CLK INPUT

RESET INPUT

Q

JKFF

CLRN

Q

AND2 JKFF

PRN

OUTPUT

Q1

Q2

J

VCC

Synchronous Counter with Asynchronous Reset

Figure 7.58 shows a set of simulation waveforms that illustrate the asynchronous clear

function. When RESET is HIGH, the count proceeds normally. The positive clock edge at

440 ns drives the counter to state 011. The reset pulse at 460 ns sets the counter to 000 as

soon as it goes LOW. On the next clock edge, the count proceeds from 000.

The function that sets all flip-flops in a circuit to a known initial state is sometimes

called Master Reset.

❘❙❚ SECTION 7.5 REVIEW PROBLEM

7.5 What is the main difference between synchronous and asynchronous circuits, such as

the two counters in Figures 7.49 and 7.53? What disadvantage is there to an asynchronous

circuit?

7.6 Edge-Triggered T Flip-Flops

T (toggle) flip-flop A flip-flop whose output toggles between HIGH and LOW

states on each applied clock pulse when a synchronous input, called T, is active.

In the section on the JK flip-flop, we saw how that device can be set to toggle between

HIGH and LOW output states. Other types of flip-flops can perform this function, as well.

For example, Figure 7.59 shows a D flip-flop configured for toggle operation. Since Q follows

D and D _ Q_ in this circuit, then the flip-flop output must change to its opposite state

with each clock pulse. Figure 7.60 shows a MAX_PLUS II simulation of this circuit.

K E Y T E R M

Q

DFF

D

CLRN

CLK INPUT

OUTPUT Q

FIGURE 7.59

D Flip-Flop Configured for Toggle Function

➥ notg2d.gdf

notg2d.scf

FIGURE 7.58

Simulation of Synchronous Counter with Asynchronous Reset

It is seldom useful for flip-flops in synchronous circuits to be permanently configured

in toggle mode. What made the JK flip-flops suitable elements for the synchronous counter

in Figure 7.53 was the fact that sometimes they toggled and sometimes they didn’t, depending

on the current point in the output sequence of the counter. Figure 7.61 shows a D

flip-flop configured for a switchable toggle function.

Simulation of D Flip-Flop in Toggle Mode

Q

DFF

D

CLRN

CLK INPUT

T INPUT

OUTPUT Q

Switchable Toggle Function for

a D Flip-Flop

The XOR gate acts as an inverter when the T input is HIGH and as a noninverting

buffer when T is LOW. Thus, when T is LOW, the Q output is circulated back to the D input

of the flip-flop and the current value of Q is reloaded on the next clock pulse. When T

is HIGH, the circuit acts like that of Figure 7.59 and toggles.

A T flip-flop has this equivalent function. Figure 7.62 shows the symbol of a T flipflop

in a MAX_PLUS II Graphic Design File. A MAX_PLUS II simulation in Figure

7.63 shows the operation of this device. The Q output toggles on each clock pulse when

➥ d_toggle.gdf

d_toggle.scf

➥ t_flipflop.gdf

Q

TFF

CLRN

CLK INPUT

T INPUT OUTPUT Q

FIGURE 7.62

T Flip-Flop

Simulation of T Flip-Flop

in Table 7.10.

Flip-Flop

↑0 Qt No Change

↑1 Q_t Toggle

0 X Qt Inhibited

1 X Qt Inhibited

↓X Qt Inhibited

❘❙❚ SECTION 7.6 REVIEW PROBLEM

7.6 Draw a circuit showing how the JK flip-flops in Figure 7.53 can be replaced by T flipflops.

stable before a CLK pulse is applied.

stable after the active CLK transition is finished.

pulse to the midpoint of the trailing edge.

states after a change at one or more of its inputs.

Flip-flops are electrical devices with inherent internal switching delays. As such, they have

specific requirements for the timing of the input and output waveforms in order for them to

operate reliably. We will examine the basic timing requirements for two small scale integration

(SSI) devices: the 74LS107A JK flip-flop (LSTTL family) and the 74HC107 JK

flip-flop (high-speed CMOS family). Figure 7.64 shows some of the basic timing requirements

of a JK flip-flop.

Figure 7.64a illustrates the definitions of setup time (tsu), hold time (th), and pulse

width (tW). The notation used for the “J or K” waveform indicates that the J or K input

could be at either logic level and makes a transition to the opposite level at some point. The

setup time is measured from the midpoint of the J or K transition to the midpoint of the active

CLK edge. The logic level on the J or K input must be steady for at least this time for

the flip-flop to operate correctly. Setup time for both LSTTL and high-speed CMOS flipflops

is about 20 ns.

Similarly, the hold time is measured from the midpoint of the CLK transition to the

midpoint of the next J or K transition. The J or K level must be held steady for at least this

time to ensure dependable operation. Hold time is 0 for LSTTL and 3 ns for a high-speed

CMOS flip-flop.

The pulse width, tw, shows how long the CLK needs to be held LOW after an active

logic levels must reach a steady state before the device can accept a new clock pulse. This

K E Y T E R M S

7.7 • Timing Parameters 313

minimum pulse width allows the necessary time for these internal transitions. The data

sheet for a 74HC107 flip-flop (high-speed CMOS) gives the clock pulse width as 16 ns; a

data sheet for a 74LS107A device gives the value as 20 ns.

Figure 7.64b shows the pulse width required at the C_L_R_ input, the propagation delay

from C_L_R_ to Q and Q_, and the recovery time that must be allowed from the end of a C_L_R_

pulse to the beginning of a CLK pulse. These times also apply to a pulse on the P_R_E_ input

of a flip-flop.

Propagation delay is the result of internal electrical delays, primarily the charging and

discharging of internal capacitances of the gate transistor junctions. The practical result of

this is that a pulse at the C_L_R_ input makes Q go LOW, but not immediately; there is a

delay of several nanoseconds between input pulse and output response.

Propagation delay is defined by the direction of the output transition. The delay at Q,

which goes from HIGH to LOW, is called tpHL. The delay at Q_, which goes from LOW to

HIGH when cleared, is called tpLH. Values for propagation delay from C_L_R_ to Q or Q_ are

about 20 ns for LSTTL and 31 ns for high-speed CMOS.

The recovery time, trec, allows the internal logic levels of the flip-flop to reach a steady

state after a C_L_R_ pulse. When the internal levels are stable, the device is ready to accept an

active CLK edge. The recovery time for high-speed CMOS is 20 ns and 25 ns for an

LSTTL device. (The LSTTL data sheet treats this parameter as a species of setup time; it is

shown as setup time after the C_L_R_ is inactive. Same thing.)

Finally, Figure 7.64c shows the propagation delay from CLK to Q. This is the time

from the midpoint of an active CLK edge to the midpoint of a transition at Q caused by that

CLK edge. The parameters are defined, as before, by the direction of the output transition.

Propagation delays tpLH and tpHL are 20 ns, maximum, for a 74LS107A device and 25 ns

for a 74HC107 flip-flop.