Chapter 1 Basic Principles of Digital Systems outlin e 1

57 41 52 4E 49 4E 47 21 20 54 68 69 73 20 63 6F 6D

6D 61 6E 64 20 65 72 61 73 65 73 20 36 34 30 4D 20

6F 66 20 6D 65 6D 6F 72 79 2E

derive the Boolean expressions for both Co (carry output)

and _ (sum output) in terms of inputs A and B. Draw the

half adder circuit.

derive the simplest possible Boolean expressions for

circuit showing a full adder constructed from two half

adders.

6.19 Evaluate the Boolean expression for _ and COUT of

the full adder in Figure 6.7 for the following input

values. What is the binary value of the outputs in each

case?

6.10, as follows. Determine the output of each full adder

based on the inputs shown below. Calculate each sum

manually and compare it to the 5-bit output

(C4 _4 _3 _2 _1) of the parallel adder circuit.

a. A4 A3 A2 A1 _ 0100, B4 B3 B2 B1 _ 1001

b. A4 A3 A2 A1 _ 1010, B4 B3 B2 B1 _ 0110

c. A4 A3 A2 A1 _ 0101, B4 B3 B2 B1 _ 1101

d. A4 A3 A2 A1 _ 1111, B4 B3 B2 B1 _ 0111

6.21 Briefly describe the differences in the underlying design

strategies of the ripple carry adder and the fast carry

adder (i.e., what makes the fast carry faster than the ripple

carry?). What is the main limitation for the fast carry circuit?

to generate Boolean expression for C1, C2, and C3 for a

fast carry adder.

6.23 The following equation describes the carry output function

for a parallel binary adder:

_ A2 B2 (A4 _ B4)(A3 _ B3)

_ A1 B1 (A4 _ B4)(A3 _ B3)(A2 _ B2)

_ CIN (A4 _ B4)(A3 _ B3)(A2 _ B2)

(A1 _ B1)

Briefly explain how to interpret the third term of this

equation.

6.24 Write a VHDL file for an 8-bit parallel adder, using eight

instances of a full adder component.

showing a representative sample of sums. How many different

sums would be required to show all possible combinations

of inputs?

GENERATE statement.

6.26 showing only one transition, as follows. Set input a

to 000 from 0 to 500 ns, then 001 from 500 ns to 1 _s.

Set input b to FFF from 0 to 1 _s. From the simulation,

determine the internal delays from a1 to each of the sum

bits. Confirm your observations with the delay matrix

from a timing analysis.

6.28 Use MAX_PLUS II to create a Graphic Design File for a

2’s complement subtractor based on a 4-bit parallel binary

adder. Explain how the circuit generates the 2’s

complement of B for the subtraction A _ B.

2’s complement adder/subtractor based on a 4-bit parallel

binary adder. Explain how the circuit is programmed to

add or subtract and how it produces the 2’s complement

of B for the subtraction A _ B.

6.30 Use MAX_PLUS II to draw a circuit that will detect an

overflow condition in a 4-bit 2’s complement adder/

subtractor. The detector output should go HIGH upon

overflow detection. Draw the circuit truth table, explain

what all input and output variables are, and show any

Boolean equations you need to complete the circuit design.

include an overflow detection circuit.

overflow detection (Problem 6.31), using the following

representative hexadecimal input values: F _ 1 _ 10

(carry, but no overflow); 7 _ 1 _ 8 (overflow, but no

carry); 8 _ 8 _ 10 (carry and overflow); 0 _ 1 _ F (result

__1).

adder/subtractor (addsub4g.vhd) to include an overflow

detection circuit. Use two different methods.

6.34 What is the permissible range of values that a sum or difference,

x, can have in a 16-bit parallel binary adder if it

is written as:

a. A signed binary number

b. An unsigned binary number

numbers plus an input carry? How many digits are

needed to display the result?

6.36 What is the maximum BCD sum of two 4-digit BCD

numbers plus an input carry? How many digits are

needed to display the result?

6.37 Based on the answers to Problems 6.35 and 6.36, formulate

a general rule to calculate the maximum BCD sum of

two n-digit BCD numbers plus a carry bit.

6.38 Derive the Boolean expression for a BCD carry output as

a function of the sum of two BCD digits.

converter for a BCD adder. Use a selected signal assignment

or CASE statement.

6.41 Write a VHDL file that uses the binary-to-BCD code converter

of Problem 6.40 and a 4-bit parallel binary adder as

components in a BCD adder.

6.42 Write a VHDL file that uses a code converter and parallel

adder as components in a design that will add two 2-digit

BCD numbers and produce a 21⁄2 digit result.

6.43 Draw the block diagram of a circuit that will add two

3-digit BCD numbers and display the result as a series

of decimal digits. How many digits will the output display?

A N S W E R S T O S E C T I O N R E V I E W P R O B L E M S

6.1 101000; 6.2 100000.

6.3 11; 6.4 1

6.5 11100000; 6.6 100000.

6.7a 11701H 6.7b 1281H

6.8 “True or False: 1/4 _ 1/2”

6.9 Figures 6.32 and 6.33 show the propagation paths for the

carry bits.

Fast carry: 3 gates

Ripple carry: 8 gates

Section 6.6b

6.10a Signed: _2048 _ x __2047 (11 magnitude bits, 1 sign

bit)

6.10b Unsigned: 0 _ x __4095 (12 magnitude bits, no sign

6.11 Maximum BCD sum _ 1001 1001 1001 _ 1001 1001

1001 _ 1 1001 1001 1000BCD _ 199810. This sum requires a

3_

1

_-digit numerical display.

Answers to Section Review Problems 273

INPUT

a1

c1 c1

AND2

OR2

a2 INPUT

AND2

a3 INPUT

AND2

a4 INPUT

AND2

c0 INPUT

OR3

AND2

OR6

VCC

AND4

AND2

AND4

c4 OUTPUT c4

Fast Carry from A4/B4 to C4.

C0

C4

A1 _ B1

A2 _ B2

A3 _ B3

A4 _ B4

Ripple Carry from C0 to C4

❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚

❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚

C H A P T E R 7

Introduction to Sequential Logic

O U T L I N E

7.1 Latches

7.2 NAND/NOR Latches

7.3 Gated Latches

7.4 Edge-Triggered D

Flip-Flops

Flip-Flops

Flip-Flops

C H A P T E R O B J E C T I V E S

Upon successful completion of this chapter, you will be able to:

• Explain the difference between combinational and sequential circuits.

• Define the set and reset functions of an SR latch.

• Draw circuits, function tables, and timing diagrams of NAND and NOR

latches.

• Explain the effect of each possible input combination to a NAND and a

NOR latch, including set, reset, and no change functions, as well as the ambiguous

or forbidden input condition.

• Design circuit applications that employ NAND and NOR latches.

• Describe the use of the ENABLE input of a gated SR or D latch as an enable/

inhibit function and as a synchronizing function.

• Outline the problems involved with using a level-sensitive ENABLE input

on a gated SR or D latch.

• Explain the concept of edge-triggering and why it is an improvement over

level-sensitive enabling.

• Draw circuits, function tables, and timing diagrams of edge-triggered D,

JK, and T flip-flops.

• Describe the toggle function of a JK flip-flop and a T flip-flop.

• Describe the operation of the asynchronous preset and clear functions of D,

JK, and T flip-flops and be able to draw timing diagrams showing their

functions.

• Use MAX_PLUS II to create simple circuits and simulations with D

latches and D, JK, and T flip-flops.

• Create simple flip-flop designs using VHDL.

The digital circuits studied to this point have all been combinational circuits, that is, circuits

whose outputs are functions only of their present inputs. A particular set of input

states will always produce the same output state in a combinational circuit.

276 C H A P T E R 7 • Introduction to Sequential Logic

This chapter will introduce a new category of digital circuitry: the sequential circuit.

The output of a sequential circuit is a function both of the present input conditions and the

previous conditions of the inputs and/or outputs. The output depends on the sequence in

which the inputs are applied.

We will begin our study of sequential circuits by examining the two most basic sequential

circuit elements: the latch and the flip-flop, both of which are part of the general

class of circuits called bistable multivibrators. These are similar devices, each being used

to store a single bit of information indefinitely. The difference between a latch and a flipflop

is the condition under which the stored bit is allowed to change.

Latches and flip-flops are also used as integral parts of more complex devices, such as

programmable logic devices (PLDs), usually when an input or output state must be stored.

_

7.1 Latches

Sequential circuit A digital circuit whose output depends not only on the present

combination of inputs, but also on the history of the circuit.

the latch store a logic 0 (reset) or 1 (set) until actively changed.

2. A latch input that makes the latch store a logic 1.

2. A latch input that makes the latch store a logic 0.

All the circuits we have seen up to this point have been combinational circuits. That is,

their present outputs depend only on their present inputs. The output state of a combinational

circuit results only from a combination of input logic states.

The other major class of digital circuits isthe sequential circuit. The present outputs

of a sequential circuit depend not only on its present inputs, but also on its past input states.

The simplest sequential circuit is the SR latch, whose logic symbol is shown in Figure

7.1a. The latch has two inputs, SET (S) and RESET (R), and two complementary outputs,

Q and Q_. If the latch is operating normally, the outputs are always in opposite logic states.

K E Y T E R M S

SR Latch (Active HIGH Inputs)

The latch operates like a momentary-contact pushbutton with START and STOP functions,

shown in Figure 7.2. A momentary-contact switch operates only when it is held

down. When released, a spring returns the switch to its rest position.

Suppose the switch in Figure 7.2 is used to control a motor starter. When you push the

START button, the motor begins to run. Releasing the START switch does not turn the

motor off; that can be done only by pressing the STOP button. If the motor is running,

pressing the START button again has no effect, except continuing to let the motor run. If

the motor is not running, pressing the STOP switch has no effect, since the motor is already

stopped.

trying to start and stop the motor at the same time. We will come back to this point

later.

The latch SET input is like the START button in Figure 7.2. The RESET input is like

By definition:

A latch is set when Q _ 1 and Q_ _ 0.

A latch is reset when Q _ 0 and Q_ _ 1.

The latch in Figure 7.1 has active-HIGH SET and RESET inputs. To set the latch, make

R _ 0 and make S _ 1. This makes Q _ 1 until the latch is actively reset, as shown in the

timing diagram in Figure 7.1b. To activate the reset function, make S _ 0 and make R _ 1.

The latch is now reset (Q _ 0) until the set function is next activated.

Combinational circuits produce an output by combining inputs. In sequential circuits,

it is more accurate to think in terms of activating functions. In the latch described, S and R

are not combined by a Boolean function to produce a particular result at the output. Rather,

the set function is activated by making S _ 1, and the reset function is activated by making

R _ 1, much as we would activate the START or STOP function of a motor starter by

pressing the appropriate pushbutton.

The timing diagram in Figure 7.1b shows that the inputs need not remain active after

the set or reset functions have been selected. In fact, the S or R input must be inactive before

the opposite function can be applied, in order to avoid conflict between the two functions.

❘❙❚ EXAMPLE 7.1 Latches can have active-HIGH or active-LOW inputs, but in each case Q _ 1 after the set

function is applied and Q _ 0 after reset. For each latch shown in Figure 7.3, complete the

timing diagram shown. Q is initially LOW in both cases. (The state of Q before the first active

history of the circuit.)

Industrial Pushbutton (e.g.,

Motor Starter)

FIGURE 7.3

Example 7.1

SR Latch

278 C H A P T E R 7 • Introduction to Sequential Logic

SOLUTION The Q and Q_ waveforms are shown in Figure 7.3. Note that the outputs respond

only to the first set or reset command in a sequence of several pulses.

❘❙❚ EXAMPLE 7.2 Figure 7.4 shows a latching HOLD circuit for an electronic telephone. When HIGH, the

HOLD output allows you to replace the handset without disconnecting a call in progress.

FIGURE 7.4

Example 7.2

Latching HOLD Button

The two-position switch is the telephone’s hook switch (the switch the handset pushes

down when you hang up), shown in the off-hook (in-use) position. The normally closed

pushbutton is a momentary-contact switch used as a HOLD button. The circuit is such that

the HOLD button does not need to be held down to keep the HOLD active. The latch “remembers”

that the switch was pressed, until told to “forget” by the reset function.

Describe the sequence of events that will place a caller on hold and return the call

from hold. Also draw timing diagrams showing the waveforms at the HOLD input, hook

switch inputs, S input, and HOLD output for one hold-and-return sequence. (HOLD output

_ 1 means the call is on hold.)

hold the HOLD switch, then the hook switch. This combines two HIGHs—one from the

making S _ 1 and R _ 0. Note the sequence of events: press HOLD, hang up, release

be kept on-hook and the HOLD button released. The latch stays set, as S _ R _ 0 (neither

To restore a call, lift the handset. This places the hook switch into the off-hook position

and now S _ 0 and R _ 1, which resets the latch and turns off the HOLD condition.

Figure 7.5 shows the timing diagram for the sequence described.

Example 7.2

HOLD Timing Diagram

❘❙❚

❘❙❚ SECTION 7.1 REVIEW PROBLEM

7.1 A latch with active-HIGH S and R inputs is initially set. R is pulsed HIGH three times,

with S _ 0. Describe how the latch responds.

An SR latch is easy to build with logic gates. Figure 7.6 shows two such circuits, one made

from NOR gates and one from NANDs. The NAND gates in the second circuit are drawn

in DeMorgan equivalent form.

SR Latch Circuits

The two circuits both have the following three features:

1. OR-shaped gates

2. Logic level inversion between the gate input and output

3. Feedback from the output of one gate to an input of the opposite gate

During our examination of the NAND and NOR latches, we will discover why these

features are important.

A significant difference between the NAND and NOR latches is the placement of SET

and RESET inputs with respect to the Q and Q_ outputs. Once we define which output is

In a NOR latch, the gates have active-HIGH inputs and active-LOW outputs. When the

input to the Q gate is HIGH, Q _ 0, since either input HIGH makes the output LOW.

Therefore, this input must be the RESET input. By default, the other is the SET input.

In a NAND latch, the gate inputs are active LOW (in DeMorgan equivalent form) and

the outputs are active HIGH. A LOW input on the Q gate makes Q _ 1. This, therefore, is

the SET input, and the other gate input is RESET.

Since the NAND and NOR latch circuits have two binary inputs, there are four possible

input states. Table 7.1 summarizes the action of each latch for each input combination.

The functions are the same for each circuit, but they are activated by opposite logic levels.

0 0 Neither SET nor RESET 0 0 Both SET and RESET

active; output does not active; forbidden condichange

from previous tion

state

0 1 RESET input active 0 1 SET input active

1 1 Both SET and RESET 1 1 Neither SET nor RESET

active; forbidden condi- active; output does not

tion change from previous

state

280 C H A P T E R 7 • Introduction to Sequential Logic

We will examine the NAND latch circuit for each of the input conditions in Table 7.1.

The analysis of a NOR latch is similar and will be left as an exercise.

NAND Latch Operation

Figure 7.7 shows a NAND latch in its two possible stable states. In each case the inputs S_

and R_ are both HIGH (inactive).

S _ 1

Q 1

_

0

Q _ 0 Q _ 1

S _ 1

0

_

R _ 1

NAND Latch Stable States

Figure 7.7a shows the latch in its SET condition (Q _ 1). The feedback connections

from each gate output to the input of the opposite gate keep the latch in a stable condition.

The upper gate has a LOW on the “inner” input. Since, for a NAND gate, either input LOW

makes the output HIGH, this makes Q _ 1. This HIGH value is fed to the gate on the other

side of the latch. The lower gate has both inputs HIGH, thus keeping its output LOW. The

LOW at Q_ feeds back to the upper gate, forming a closed loop of consistent logic levels.

There is no tendency for the outputs to change under these conditions.

Figure 7.7b shows a similar state for the latch in a RESET condition (Q _ 0). As with

the SET state, the stability of the latch depends on the feedback connections. The logic values

of the latch gate inputs are the same as before, except that the LOW input is on the

lower gate, not the upper gate as in the SET condition.

Figure 7.8 shows a NAND latch as a Graphic Design File created with MAX_PLUS

II. The inputs are labeled nS and nR and one output as nQ as we cannot enter input names

with bars over them. (BOR2 _ “Bubbled OR, 2-inputs”.)

nS

INPUT

OUTPUT

BOR2

nR

Q