Table 7.5 Function Table of a Transparent Latch EN D Q

0 X Qt Q_t No Change Store

1 0 0 1 Reset Transparent

1 1 1 0 Set

Implementing D Latches in MAX_PLUS II

A D latch can be implemented in MAX_PLUS II as a primitive in a Graphic Design File

or in a VHDL design entity. It can also be created with a behavioral or structural description

in a VHDL file.

Figure 7.31 shows a D latch primitive in a MAX_PLUS II Graphic Design File. Figure

7.32 shows a simulation of the latch. From 0 to 500 ns, ENABLE is HIGH and the latch

is in the transparent mode (Q follows D). When ENABLE goes LOW, the last value of D (0)

is stored until ENABLE goes high again, just before 800 ns. When ENABLE goes LOW

again, a new value of D (1) is stored until the end of the simulation.

Q

LATCH

ENA INPUT

OUTPUT Q

D

ENA

D-Latch in a MAX_PLUS II Graphic Design File

Simulation for a D Latch

➥ d_latch.gdf

d_latch.scf

InVHDL, a PROCESS statement is concurrent, but the statements inside the PROCESS

are sequential. In otherwords, anything described by a PROCESSacts like a separate component

in a design entity.However, the interior of the component so described acts as a sequential

circuit. Since the behavior of aDlatch is sequential, its description can be created inside a

PROCESS. (You can pull a latch out of a bin of parts and connect it in a circuit, but the inside

of the part is sequential.) The following VHDL code describes a D latch.

—— d_lch.vhd

—— D latch with active-HIGH level-sensitive enable

ENTITY d_lch IS

PORT(

d, ena : IN BIT;

END d_lch;

ARCHITECTURE a OF d_lch IS

BEGIN

BEGIN

q __ d;

END PROCESS;

END a;

➥ d_lch.vhd

Another method, recommended by the MAX_PLUS II documentation, is to instantiate

a LATCH primitive in a VHDL file. The primitive is contained in the altera library, in

a package called maxplus2. The component declaration for this primitive is:

COMPONENT LATCH

PORT (d : IN STD_LOGIC;

ena : IN STD_LOGIC;

q : OUT STD_LOGIC);

END COMPONENT;

Since the component declaration is in the maxplus2 package, you do not have to declare

it in the file in which you are using it. A VHDL file that uses the latch primitive is

listed next. The component declaration uses STD LOGIC types, so we must include the

type definitions in the ieee library (std_logic_1164 package).

—— lch_prim.vhd

—— D latch with active-HIGH level-sensitive enable

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

LIBRARY altera;

USE altera.maxplus2.ALL;

ENTITY lch_prim IS

PORT(

d_in, enable : IN STD_LOGIC;

END lch_prim;

ARCHITECTURE a OF lch_prim IS

BEGIN

latch_primitive: latch

PORT MAP (d __ d_in,

ena __ enable,

q __ q_out);

END a;

Help. In the Help menu, select Primitives. By clicking on the name of a particular primitive,

you can determine whether it can be instantiated in a VHDL file and what its component

declaration is, if available.

❘❙❚ EXAMPLE 7.5 A system for monitoring automobile traffic is set up at an intersection, with four sensors,

placed as shown in Figure 7.33. Each sensor monitors traffic for a particular direction.

When a car travels over a sensor, it produces a logic HIGH. The status of the sensor system

➥ lch_prim.vhd

Example 7.5

Sensor Placement in a Traffic

Intersection

is captured for later analysis by a set of D latches, as shown in Figure 7.34. A timing pulse

enables the latches once every five seconds and thus stores the system status as a “snapshot”

of the traffic pattern.

Figure 7.35 shows the timing diagram of a typical traffic pattern at the intersection.

The D inputs show the cars passing through the intersection in the various lanes. Complete

this timing diagram by drawing the Q outputs of the latches.

How should we interpret the Q output waveforms?

1

ENA

Timing

D1 Q1

ENA

3

ENA

4

ENA

Q1

Q2

Q4 Q4

Example 7.5

D Latch Collection of Data

FIGURE 7.35

Example 7.5

Latch Configuration and Timing

Diagram

synchronizes the random sensor pattern to a 5-second standard interval. A HIGH on any Q

output indicates a car over a sensor at the beginning of the interval. For example, at the

beginning of the first interval, there is a car in the northbound lane (Q1) and one in the

southbound lane (Q2). Similar interpretations can be made for each interval.

❘❙❚

for which certain properties can be specified when the component is instantiated.

specified when the component is instantiated.

to a value for that instance of the component.

name of a port, variable, or signal in a design entity that uses the component.

We can easily use VHDL to implement latches with multiple D inputs and Q outputs, but

with a common ENABLE line, as in Figure 7.34. Three approaches are:

1. Use a behavioral description, as we did earlier for a single latch (d_lch.vhd). Use

STD_LOGIC_VECTOR types for D and Q, rather than STD_LOGIC.

2. Altera recommends using a latch primitive or predefined component, rather than creating

your own latch structures. We can use multiple LATCH primitives, instantiated

by a GENERATE statement, as we did for multiple instances of a full adder in

Chapter 6.

3. Use a latch component from the Library of Parameterized Modules (LPM). These

components are specified in the lpm_components package in the lpm library.

Certain properties of an LPM component, such as the number of inputs or outputs,

can be specified when the component is instantiated. These properties are referred to as

and input four bits wide, we set the parameter called LPM_WIDTH to a value of 4.

The various parameters of an LPM component can be found in the LPM Quick Reference

on the CD that accompanies this book or in the MAX_PLUS II Help menu under

An input or output of an LPM component is called a port. A port map is used to make

a correspondence between the port names in the component declaration and the port names

used in the file containing the component. Since LPM components are declared in a separate

package, we must refer to the MAX_PLUS II Help or the LPM Quick Reference to

determine the port names for a component. LPM components are instantiated the same as

any other component.

The three VHDL files that follow each specify a 4-bit latch with common enable, each

using one of the above methods.

Behavioral Description:

—— ltch4bhv.vhd

—— D latch with active-HIGH level-sensitive enable

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

K E Y T E R M S

ENTITY ltch4bhv IS

PORT(d : IN STD_LOGIC_VECTOR (3 downto 0);

enable : IN STD_LOGIC;

q : OUT STD_LOGIC_VECTOR (3 downto 0));

END ltch4bhv;

ARCHITECTURE a OF ltch4bhv IS

BEGIN

BEGIN

q __ d;

END PROCESS;

END a;

4 LATCH Primitives and a GENERATE Statement:

—— ltch4prm.vhd

—— D latch with active-HIGH level-sensitive enable

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

LIBRARY altera;

USE altera.maxplus2.ALL;

ENTITY ltch4prm IS

PORT(d_in : IN STD_LOGIC_VECTOR (3 downto 0);

enable : IN STD_LOGIC;

q_out : OUT STD_LOGIC_VECTOR (3 downto 0));

END ltch4prm;

ARCHITECTURE a OF ltch4prm IS

BEGIN

latch4:

latch_primitive: latch

PORT MAP (d __ d_in (i), ena __ enable, q __ q_out (i));

END GENERATE;

END a;

LPM Latch:

—— ltch4lpm.vhd

—— 4-BIT D latch with active-HIGH level-sensitive enable

—— Uses a latch component from the Library of Parameterized

—— Modules (LPM)

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

LIBRARY lpm;

USE lpm.lpm_components.ALL;

ENTITY ltch4lpm IS

PORT(d_in : IN STD_LOGIC_VECTOR (3 downto 0);

enable : IN STD_LOGIC;

q_out : OUT STD_LOGIC_VECTOR (3 downto 0) );

END ltch4lpm;

➥ ltch4bhv.vhd

➥ ltch4prm.vhd

➥ ltch4lpm.vhd

ltch4lpm.scf

298 C H A P T E R 7 • Introduction to Sequential Logic

ARCHITECTURE a OF ltch4lpm IS

BEGIN

—— Instantiate latch from an LPM component

GENERIC MAP (LPM_WIDTH __ 4)

PORT MAP (data __ d_in,

gate __ enable,

q __ q_out);

END a;

count, from 5 to C (0101 to 1100) is applied to d_in. This count contains both states (0 and

1) for each input bit. For each applied input state, the output bus, q_out, does not change

until the enable line goes HIGH.

Simulation of a 4-bit D Latch

❘❙❚ SECTION 7.3 REVIEW PROBLEM

7.3 Write the VHDL code for a 16-bit latch with common active-HIGH enable, using

MAX_PLUS II latch primitives.

7.4 Edge-Triggered D Flip-Flops

Edge The HIGH-to-LOW (negative edge) or LOW-to-HIGH (positive edge) transition

of a pulse waveform.

negative-going edge of a waveform.

In Example 7.4, we saw how a shorter pulse width at the ENABLE input of a gated latch increased

the chance of the output being synchronized to the ENABLE pulse waveform. This

is because a shorter ENABLE pulse gives less chance for the SET and RESET inputs to

change during the time the latch is enabled.

A logical extension of this idea is to enable the latch for such a small time that the

width of the ENABLE pulse is almost zero. The best approximation we can make to this is

to allow changes to the circuit output only when an enabling, or CLOCK, input receives the

K E Y T E R M S

LOW to HIGH (positive edge) or HIGH to LOW (negative edge), as shown in Figure 7.37.

We can say that a device enabled by an edge is edge-triggered or edge-sensitive.

FIGURE 7.37

Edges of a CLOCK Waveform

Since the CLOCK input enables a circuit only while in transition, we can refer to it as

a “dynamic” input. This is in contrast to the ENABLE input of a gated latch, which is levelsensitive

or “static,” and will enable a circuit for the entire time it is at its active level.

Latches vs. Flip-Flops

edge of a CLOCK input to an active-level pulse at the internal latch’s SET and RESET

inputs.

A gated latch with a clock input is called a flip-flop. Although the distinction is not always

latch) or no enable (e.g., NAND latch) and a flip-flop as a circuit with an edge-triggered

definition this is not correct, since neither of these circuits has a clock input. (An SR flip-flop

would be like the gated SR latch of Figure 7.27 with a clock instead of an enable input.)

The symbol for the D, or data, flip-flop is shown in Figure 7.38. The D flip-flop has

the same behavior as a gated D latch, except that the outputs change only on the positive

edge of the clock waveform, as opposed to the HIGH state of the enable input. The triangle

on the CLK (clock) input of the flip-flop indicates that the device is edge-triggered.

Table 7.6 shows the function table of a positive edge-triggered D flip-flop.

Figure 7.39 shows the equivalent circuit of a positive edge-triggered D flip-flop. The

circuit is the same as the transparent latch of Figure 7.29, except that the enable input

(called CLK in the flip-flop) passes through an edge detector, a circuit that converts a positive

edge to a brief positive-going pulse. (A negative edge detector converts a negative

edge to a positive-going pulse.)

K E Y T E R M

D Flip-Flop Logic Symbol

Edge-Triggered D Flip-Flop

↑0 0 1 Reset

↑1 1 0 Set

0 X Qt Q_t Inhibited

1 X Qt Q_t Inhibited

↓X Qt Q_t Inhibited

D Flip-Flop Equivalent Circuit

Figure 7.40 shows a circuit that acts as a simplified positive edge detector. Edge detection

depends on the fact that a gate output does not switch immediately when its input

switches. There is a delay of about 3 to 10 ns from input change to output change, called

propagation delay.

FIGURE 7.40

Positive Edge Detector

Operation of a D Flip-Flop

When input x, shown in the timing diagram of Figure 7.40, goes from LOW to HIGH,

the inverter output, x_, goes from HIGH to LOW after a short delay. This delay causes both

following the positive edge at x.

When x returns to LOW, x_ goes HIGH after a delay. However, there is no time in this

sequence when both AND inputs are HIGH. Therefore, the circuit output stays LOW after

the negative edge of the input waveform.

Figure 7.41 shows how the D flip-flop circuit operates. When D _ 0 and the edge detector

senses a positive edge at the CLK input, the output of the lower NAND gate steers a

low-going pulse to the RESET input of the latch, thus storing a 0 at Q. When D _ 1, the upper

NAND gate is enabled. The edge detector sends a high-going pulse to the upper steering

gate, which transmits a low-going SET pulse to the output latch. This action stores a

1 at Q.

7.4 • Edge-Triggered D Flip-Flops 301

❘❙❚ EXAMPLE 7.6 Figure 7.42 shows a MAX_PLUS II Graphic Design File with a D latch and a D flipflop

connected to the same data input and clock. Create a MAX_PLUS II simulation that

illustrates the difference between the latch (level-sensitive enable) and the flip-flop (edgetriggered

clock).

Q

DFF

D

CLRN

Q

LATCH

CLK INPUT

OUTPUT Q_latch

D

ENA

D Latch and D Flip-Flop

on the waveform indicate the similarities and differences between the latch and flip-flop

operation.

FIGURE 7.43

Simulation showing the Difference between D Latch and D Flip Flop

1. At 1.2 _s, D goes HIGH. The latch output (Q_latch) and the flip-flop output

(Q_ flip_ flop) both go HIGH at 1.4 _s, since the beginning of the enable HIGH state

and the positive edge of the CLK both correspond to this time.

2. D goes LOW at 2 _s. Both Q outputs go LOW at 2.8 _s since the positive edge of the

CLK and its HIGH level occur at the same time.

3. The D input goes HIGH at 4.4 _s, in the middle of a CLK pulse. Since the CLK line is

HIGH, Q_ latch changes immediately. Q_ flip_ flop does not change until the next positive

edge, at 6 _s.

4. D goes LOW at 7.8 _s. Q_latch also changes at this time, since CLK is HIGH.

Q_ flip_ flop changes on the next positive edge, at 9.2 _s.

❘❙❚

Note that the latch output is in an unknown state until the first CLK pulse, whereas the

flip-flop output is LOW, even before the first CLK pulse. This is because Altera CPLDs

have power-on reset circuitry that ensures that flip-flop outputs in a CPLD are LOW immediately

after power is applied to the device. The MAX_PLUS II simulator accounts for

this condition.

❘❙❚ EXAMPLE 7.7 Two positive edge-triggered D flip-flops are connected as shown in Figure 7.44a. Inputs D0

and CLK are shown in the timing diagram. Complete the timing diagram by drawing the

waveforms for Q0 and Q1, assuming that both flip-flops are initially reset.

FIGURE 7.44

Example 7.7

Circuit and Timing Diagram

SOLUTION Figure 7.44b shows the output waveforms. Q0 follows D0 at each point

where the clock input has a positive edge. One result of this is that the HIGH pulse on D0

between clock pulses 5 and 6 is ignored, since D0 _ 0 on positive edges 5 and 6.

Since D1 _ Q0 and Q1 follows D1, the waveform at Q1 is the same as at Q0, but delayed

by one clock cycle. If Q0 changes due to CLK, we assume that the value of D1 is the

same as Q0 just before the clock pulse. This is because delays within the circuitry of the

flip-flops ensure that their outputs will not change for several nanoseconds after an applied

clock pulse. Therefore, the level at D1 remains constant long enough for it to be clocked

into the second flip-flop.

The data entering the circuit at D0 are moved, or shifted, from one flip-flop to the next.

This type of data movement, called “serial shifting,” is frequently used in data communication

and digital arithmetic circuits. ❘❙❚

❘❙❚ SECTION 7.4 REVIEW PROBLEM

7.4 Which part of a D flip-flop accounts for the difference in operation between a D flipflop

and a D latch? How does it work?

7.5 • Edge-Triggered JK Flip-Flops 303

7.5 Edge-Triggered JK Flip-Flops

Toggle Alternate between opposite binary states with each applied clock pulse.

A versatile and widely used sequential circuit is the JK flip-flop.

Figure 7.45 shows the logic symbols of a positive- and a negative-edge triggered JK

flip-flop. J acts as a SET input and K acts as a RESET input, with the output changing on

the active clock edge in response to J and K. When J and K are both HIGH, the flip-flop

will toggle between opposite logic states with each applied clock pulse. The function tables

of the devices in Figure 7.45 are shown in Table 7.7.

Figure 7.46 shows the simplified circuit of a negative-edge triggered JK flip-flop. The

circuit is like that of a gated SR latch with an edge detector (an SR flip-flop), except that

there are two extra feedback lines from the latch outputs to the steering gate inputs. This

extra feedback is responsible for the flip-flop’s toggling action.

Figure 7.47 illustrates how the additional two lines cause the flip-flop to toggle. The

cross-feedback from Q to K and from Q_ to J enables one, but not both, of the steering gates.

The edge detector just after the CLK input produces a short positive-going pulse upon detecting

a negative edge on the CLK waveform. The enabled steering gate complements and

transmits this pulse to the latch, activating either the set or reset function. This in turn

changes the latch state and enables the opposite steering gate.

Since all inputs of the steering gates must be HIGH to enable one of the latch functions,

K E Y T E R M