• PAL Fuse Matrix and Combinational Outputs 333

The numbering system has some potential ambiguities. For example, it is not possible

to use 16 inputs and 8 outputs in a PAL16L8 device at the same time; 6 of the inputs are

actually input/output pins. Some possible configurations are as follows:

16 inputs (10 dedicated _ 6 I/O) and 2 dedicated outputs

10 dedicated inputs and 8 outputs (2 dedicated _ 6 I/O)

12 inputs (10 dedicated _ 2 I/O) and 6 outputs (2 dedicated _ 4 I/O)

Each of the outputs of the PAL16L8 is buffered by a tristate inverter, whose ENABLE

input is controlled by its own product line. When the ENABLE line of the tristate inverter is

FIGURE 8.3

Unprogrammed PAL16L8

HIGH, the inverter output is the same as it would normally be—a logic HIGH or LOW, determined

by the state of the corresponding OR gate output.

When the ENABLE line is LOW, the inverter output is in the high-impedance state.

The output acts as an open circuit, neither HIGH nor LOW; it is as though the output was

completely disconnected from the circuit. The inverter is permanently enabled if all fuses

on the ENABLE product line are blown, and permanently disabled if these fuses are

all intact.

Published logic diagrams of PAL devices generally do not have fuses drawn on them.

This allows us to draw fuses for any application. In practice, PLDs have become too

complex to manually draw fuse maps for most applications.

Historically, PLD programming would begin with fuses drawn on a logic diagram, and

each fuse would be selected and blown individually by someone operating a hardware device

constructed for such a purpose.

Fuse assignment is nowdone with special software such asABEL, CUPL, or PALASM.

These programs will take inputs such as Boolean equations, truth tables, or other forms and

produce the simplest SOP solution to the particular problem. (MAX_PLUS II is not configured

to generate programming data for low-density PALs, although it can generate data for

similar devices in theAltera Classic PLD series.)

The end result of such software is a JEDEC file, an industry-standard way of listing

which fuses in the PLD should remain intact and which should be blown. The JEDEC file

is stored on disk as an ASCII text file. Most PLD programmers will accept the JEDEC file

and use it as a template for blowing fuses in the target device.

Fuse locations, called cells, are specified by two numbers: the product line first cell

along the top. The address of any particular fuse is the sum of its product line first cell

number and its input line number. The fuses on the PAL16L8 device are numbered from

0000 to 2047 (_ 2016 _ 31).

Figure 8.5 shows an example of a JEDEC file for a PAL16L8 application. The file

starts with an ASCII “Start Text” character (^B). Next is some information required by the

PAL programmer about the type of device (PAL16L8), number of fuses (2048), and so

forth. The fuse information starts with the line L0000, which is the first product line. The

1s and 0s which follow show the programmed state of each cell in each product line; a 1 is

a blown fuse and a 0 is an intact fuse. In other words, each 0 in the JEDEC file represents

an X in the same position on the PAL logic diagram.

The product terms for first sum-of-products output are set by the states of fuses

0000 to 0255 (eight product lines). In the file shown, all fuses are blown in the first product

I/O

PAL16L8 I/O Section

line, the second product line shows three intact fuses, and so forth. Since all fuses are

intact in the last three lines, they need not be shown in the JEDEC file.

Whenever some unprogrammed product lines are omitted from the fuse map, the last

fuse line shown ends with an asterisk (*). The next line with programmed fuses is indicated

by a new fuse number. For example, the second group of fuses (0256 to 0511) in Figure 8.5

begins after the line marked L0256 in the JEDEC file. The remaining fuse lines are

similarly indicated.

The JEDEC file in Figure 8.5 ends with a hexadecimal checksum (C8DCF), an errorchecking

code derived from the programming data, and an ASCII “End Text” code (^C).

Sample JEDEC File

In order to examine the general principle of fuse programming, let us develop the programmed

logic diagram for a common combinational circuit: a 4-to-1 multiplexer. (After

developing the fuse maps for several examples, we will not refer to this technique again.)

This circuit, shown in Figure 8.6a, directs one of four input logic signals, D0 to D3, to

output Y, depending on the state of two select inputs S0 and S1. The circuit works on the

enable/inhibit principle; each AND gate is enabled by a different combination of S1 S0. The

binary state of the select inputs is the same as the decimal subscript of the selected data

input. For instance, S1 S0 _ 10 selects data input D2; the AND gate corresponding to D2 is

enabled and the other three ANDs are inhibited.

The logic equation for output Y is given by:

Y _ D0 S_1 S_0 _ D1 S_1 S0 _ D2 S1 S_0 _ D3 S1 S0

Since the outputs of the PAL16L8 are active LOW, as illustrated in Figure 8.6b,

we should rewrite the equation as follows:

Y_ _ D_0 S_1 S_0 _ D_1 S_1 S0 _ D_2 S1 S_0 _ D_3 S1 S0

The D inputs must be complemented to reverse the effect of the active-LOW output.

The output is enabled when the EN input is HIGH. Figure 8.7 shows the PAL16L8A logic

diagram with fuses for the multiplexer application.

The multiplexer application developed in the previous section uses a PAL device whose

output is always fixed at the active-LOW polarity. This fixed polarity is suitable for most

applications, but Boolean functions that would normally have active-HIGH outputs must

be implemented in DeMorgan equivalent form, which is not always very straightforward.

Some applications require both active-HIGH and active-LOW outputs. In such cases,

it is useful to have a device whose output polarity is fuse programmable.

Figure 8.8 shows the logic diagram of a PAL20P8 PAL device. This device is the same

as a PAL16L8, except that there are four more dedicated inputs, and the polarity of each

output is programmable. The Exclusive OR gate on each output is programmed to act as either

an inverter or a buffer. When its associated fuse is intact, the XOR input is grounded

and passes the output of its related SOP network in true form. When combined with the

output inverter, this produces an active-LOW output. When the polarity fuse is blown, the

fused XOR input floats to the HIGH state, inverting the SOP output; the output pin becomes

active HIGH.

FIGURE 8.6

4-to-1 Multiplexer Circuits

The polarity fuses are given numbers higher than those of the main fuse array. In this

case, the product line fuses are numbered 0000 to 2559 and the output polarity fuses are

numbered 2560 to 2567.

Figure 8.9 illustrates the selection of output polarity. Two Boolean functions, F1 and

F2, are programmed into the fuse array, with outputs at pins (17) and (15), respectively.

The equations are:

Programmed Logic Diagram for a 4-to-1 Multiplexer

PAL20P8 Logic Diagram

We could, if we chose, rewrite F2 to show the output as active LOW:

The portion of the PAL20P8 logic diagram shown in Figure 8.9 represents the fuses

required to program F1 and F2. Pins (14) and (16) supply inputs A and B to the matrix. The

ENABLE lines of the tristate output buffers float HIGH, since all fuses are blown on the

corresponding product lines, thus permanently enabling the output buffers.

The fuses numbered 2565 and 2567 select the polarity at pins (15) and (17). Fuse

2565 is blown. The fused input to the corresponding XOR gate floats HIGH, thus making

the gate into an inverter. Combined with the tristate buffer, this makes pin (17) active

HIGH.

gate into a noninverting buffer. Combined with the tristate output buffer, this makes pin

(15) active LOW.

8.3 • PAL Outputs With Programmable Polarity 339

❘❙❚ EXAMPLE 8.1 Show how a PAL20P8 device can be used to implement the following logic functions by

drawing fuses on the device’s logic diagram.

NOT: F1 _ A_

AND: F2 _ BC

OR: F3 _ D _ E

NAND: F4 _ F_G_

NOR: F5 _ H_____J_

XOR: F6 _ K _ L _ K_ L _ K L_

XNOR: F7 _ M_______N_ _ M_ N_ _ M N

How would the implementation of these logic functions differ if only active-LOW outputs

were available, as in a PAL16L8?

can be used as inputs or outputs. Our functions need 13 input variables and 7 output

variables. We will use six I/O pins (pins (16) through (21)) and one dedicated output

(pin (15)) for the output variables.

PAL Outputs With Programmable Polarity

All functions must be in SOP form. Outputs for NOT, AND, OR, Exclusive OR, and

Exclusive NOR are active HIGH. Therefore, polarity fuses on the outputs for F1, F2, F3,

F6, and F7 are blown. NAND and NOR outputs are active LOW; the polarity fuses for F4

and F5 remain intact.

Figure 8.10 shows the logic diagram of the programmed PAL. If only active-LOW outputs

were available, we would need to rewrite some of the equations to make the outputs

correspond to their DeMorgan equivalent forms, as follows:

AND: F2 _ B_ _ C_

OR: F3 _ D_ E_

XOR: F6 _ K _ L _ K_ L_ _ K L

XNOR: F7 _ M_____N_ _ M_ N _ M N_

FIGURE 8.10

Programmed Logic Diagram for Seven Logic Functions

❘❙❚

8.4 • PAL Devices With Registered Outputs 341

8.4 PAL Devices With Registered Outputs

Register A digital circuit such as a flip-flop or array of flip-flops that stores one

or more bits of digital information.

a flip-flop (usually D-type) that stores the output state.

Flip-flops are generally found in programmable logic devices as registered outputs.

A register is one or more flip-flops used to store data. Registered outputs in programmable

array logic (PAL) devices can be used for the same functions as individual flip-flops.

Figure 8.11 shows the logic diagram of a PAL device with eight registered outputs:

a PAL16R8. The fuse matrix is identical to that of a PAL16L8 device; the differences

K E Y T E R M S

PAL16R8 Logic Diagram

Example 8.2

Rotation to the Right (4-bit Data)

between the two devices are the registered outputs, a dedicated clock input (pin 1), and a

pin for enabling all registered outputs (pin 11).

With Registered PAL, the number of outputs shown in the part number indicates the

number of registered outputs. For example, a PAL16R4 device has four registered outputs

and four combinational I/O pins, a PAL16R6 device has six registered outputs and two

combinational I/O pins, and a PAL16R8 has eight registered outputs.

❘❙❚ EXAMPLE 8.2 A common data operation is that of “rotation.” Figure 8.12 illustrates how a 4-bit number

can be rotated to the right by 0, 1, 2, or 3 places by a circuit called a “barrel shifter.”

To rotate the data, move all bits the required number of places to the right. As data reach

the rightmost position, move them to the beginning so that they are transferred in a

closed loop.

This operation is usually performed by serially shifting the data the required number

of places and feeding back the last output to the first input of a serial shift register.

Rotation can also be accomplished by a parallel transfer operation. We can load the

bits of the input into four D flip-flops in the order determined by two select inputs, S1 and

Table 8.1 summarizes the contents of the circuit after one clock pulse is applied.

0 0 A B C D 0

0 1 D A B C 1

1 0 C D A B 2

1 1 B C D A 3

Sketch a circuit, using gates and flip-flops, that can accomplish this rotation as a

parallel transfer function. Briefly explain its operation.

Write the Boolean expression(s) for the circuit.

Show how the circuit can be implemented by a PAL16R4 device by drawing fuses on

its logic diagram.

perform the specified rotation. The circuit works by enabling one AND gate in each group

of four for each combination of S1 and S0. For example, when S1 S0 _ 00, the rotation is

0 and the leftmost AND gate of each group is enabled, transferring the parallel data into

the flip-flops so that DA _ A, DB _ B, DC _ C, and DD _ D. After one clock pulse, QA

QB QC QD _ ABCD.

8.4 • PAL Devices With Registered Outputs 343

FIGURE 8.13

Example 8.2

Rotation by Parallel Transfer (Barrel Shifter)

Similarly, if S1 S0 _ 10, we select a rotation of 2. The third AND gate from the left is

selected in each group of four. This makes the data DA _ C, DB _ D, DC _ A, and DD _

B appear at the flip-flop inputs. After one clock pulse, QA QB QC QD _ CDAB.

The same principle governs the circuit operation for the other two select codes. The

Boolean equations for the circuit are:

QA _ S_1 S_0 A _ S_1 S0 D _ S1 S_0 C _ S1 S0 B

QB _ S_1 S_0 B _ S_1 S0 A _ S1 S_0 D _ S1 S0 C

QC _ S_1 S_0 C _ S_1 S0 B _ S1 S_0 A _ S1 S0 D

QD _ S_1 S_0 D _ S_1 S0 C _ S1 S_0 B _ S1 S0 A

344 C H A P T E R 8 • Introduction to Programmable Logic Architectures

FIGURE 8.14

Example 8.2

Programmed PLD for Selectable Bit Rotation

These equations imply that each registered output requires us to use four product lines,

one for each product term. The programmed logic diagram is shown in Figure 8.14. ❘❙❚

8.5 • Universal PAL and Generic Array Logic (GAL) 345

8.5 Universal PAL and Generic Array Logic (GAL)

One-time programmable (OTP) A property of some PLDs that allows them to

be programmed, but not erased.

can be configured as combinational or registered and whose programming matrix is

based on electrically erasable logic cells.

Universal PAL A PLD based on erasable cells and configurable outputs, much

like GAL, but primarily designed to emulate PAL devices, such as PAL16L8.

for a variety of input or output configurations, such as active HIGH or

active LOW, combinational or registered. Often just called a macrocell.

In-system programmability (ISP) The ability of a PLD to be programmed

through a standard four-wire interface while installed in a circuit.

(JTAG) used for loading test data or programming data into a PLD installed

in a circuit.

Architecture cell A programmable cell that, in combination with other architecture

cells, sets the configuration of a macrocell.

macrocells in a device.

macrocell only.

the device.

There are several limitations of standard low-density PALs. First, these devices are

one-time programmable (OTP). Since the AND matrix of a PAL is programmable by

blowing metal fuse links, programming is permanent; there is no opportunity to

correct or update a design. In development of a new design, where many modifications

must be made to the original design, this can be particularly wasteful. Second,

standard PAL outputs are permanently configured either as combinational or registered.

A given PAL has a certain number of each type of output, which may not be optimum

for the design. Third, a standard PAL cannot be programmed while it is installed in a

circuit.

Devices such as the PALCE16V8 Universal PAL (Vantis Corporation), and the

GAL16V8 and GAL22V10 Generic Array Logic (Lattice Semiconductor)* are based on

sum-of-products fuse matrices, just as the earlier-version PALs. However, these devices

are based on electrically erasable read only memory (EEPROM or E2PROM) cells, rather

than fuses, which allow them to be erased and reprogrammed about 10,000 times. A

programmed device will hold its data for about 20 years.

Universal PALs and GALs also have programmable input/output configurations.

An I/O pin can be configured as a registered output, a combinational output, or a

dedicated input, as required. Additionally, an output can be specified as active-HIGH or

active-LOW.

K E Y T E R M S

*Vantis has recently been acquired by Lattice, so these devices are really produced by the same

company

1 1

1 0

SL03

D Q

1 1

1 0

1 0

0 1

1 1

SG1 SL03

24 27 28 31

CLK OE

VCC

product term

Select output

enable term

Select registered or

combinational output

Select input or

feedback type

Select active

high or low

Output Logic Macrocell for a PALCE16V8 PLD

Devices such as the ispGAL22V10 or the Altera MAX7000S series can be programmed

while installed in a circuit via a standard four-wire interface called a JTAG port.

This property is known as in-system programmability (ISP).

PALCE16V8

Figure 8.15 shows one I/O pin and its associated circuitry for a PALCE16V8 Universal

PAL. (The “V” stands for “variable” or “versatile” architecture.) It consists of a programmable

SOP array with 8 product terms and an output logic macrocell (OLMC), or just

“macrocell”, which determines the I/O configuration for that pin. The various configuration

options are selected by a network of four multiplexers that are programmed by a set of

architecture cells that set the MUX select inputs HIGH or LOW.

A global architecture cell, SG1, selects configuration options for all macrocells in the

device. Two local configuration cells, SL0n and SL1n, select configurations for I/On only.

(In this case, the cells shown are SL03 and SL13 for configuration of I/O3.)

Figure 8.16 shows the different macrocell configurations for a PALCE16V8 Universal

PAL. Most of these configurations are designed to emulate an I/O of a standard PAL, so

that an old-style PAL can be replaced by a Universal PAL, and can be programmed by data

for the older PAL. The macrocells can also be configured in a pattern that does not conform

to an older device.

Figure 8.17 shows the logic diagram of a PALCE16V8 Universal PAL. The device has

eight dedicated inputs, eight macrocells, aClock pin and an Output Enable pin.The latter two

signals are shown in the macrocell diagram of Figure 8.15 as the lines labeled CLK and OE.

If there are registered outputs, the clock input (pin 1) provides a global clock function.

That is, all registered outputs are clocked simultaneously by this signal. (Some other PLDs

provide an option to clock a registered output from a product term in the AND matrix, allowing

several clock functions in one chip.) If there are no registered outputs used in the

PLD, pin 1 can be used as an input.