This paper provides information about Intel High Definition Audio (HD Audio) hardware and software on computers that run the Windows® operating system. It provides implementation guidelines for PC audio hardware designers, driver developers, solution testers, and system builders.
This information applies to the following operating systems:
Windows Server® 2008 R2
Windows Server® 2008
References and resources discussed here are listed at the end of this paper.
The current version of this paper is maintained on the Web at:
The presented information might eventually be provided in the Windows Driver Kit (WDK). If you encounter a conflict between this paper and the WDK, consider the WDK to be factually correct and this paper to be out of date.
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Function Group Level versus Widget Level Low Power Support 4
Keep Alive Enable 5
HDMI Capability Bit 5
HDMI LPCM Consolidated Audio Descriptor (CAD) 6
Digital Copyright Polarity 6
Pin Configuration Default 7
External Amplifiers 7
Digital Microphones 8
Combination Jacks 9
PC Beep 9
Hardware Stream Redirection 9
This paper presents a set of guidelines for audio hardware designers, driver developers, solution testers, and system builders to follow when they design, implement, and test Intel High Definition Audio (HD Audio) hardware and software on computers that are running the Windows® operating system. It describes the relevant behavior of Windows audio components, clarifies discrepancies and ambiguities in related specifications, and recommends methods for how to implement related functionality.
HD Audio Controller Hardware Considerations
This section provides guidance for HD Audio controller hardware designers. Cited section numbers are from the Intel HD Audio Specification 1.0. For more details, see this specification, which is listed in “Resources.”
Section 3.3.42 states that a stream descriptor’s buffer descriptor list (BDL) pointer lower base address must be 128-byte aligned. Table 1 lists the contents of the bits in a lower base address.
Table 1. Stream Descriptor n Lower Base Address
Buffer Descriptor List Lower Base Address (BDLLBASE): Lower address of the BDL. This register field must not be written when the direct memory address (DMA) engine is running or the DMA transfer could be corrupted. This value should not be modified except when the RUN bit is 0.
Hardwired to 0 to force 128-byte alignment of the BDL.
When the HD Audio controller detects violation of this alignment, it must report a descriptor error through the stream descriptor status register that is defined in section 3.3.36. Some existing controller implementations do not enforce this requirement, and in such cases hard-to-detect audio glitches occur because the DMA engine drops data.
Section 3.3.40 indicates that an HD Audio controller can update the FIFO Size field for a stream descriptor when a new data format is programmed into the stream, as follows:
“FIFO Size: This number may be static to indicate a static buffer size, or may change after the data format has been programmed if the controller is able to vary its FIFO size based on the stream format.”
Your HD Audio controller can update FIFO Size in response to stream format changes that occur only when DMA is stopped. Do not change the FIFO size of a stream descriptor while the DMA engine is running. Audio streaming software stacks rely on the FIFO size to be accurate so that they can properly track a stream’s position and perform certain DMA operations. Dynamically changing the FIFO size can adversely affect such software, leading to audio glitches.
Section 3.3.34 defines the stream descriptor control’s Traffic Priority bit as Read/Write. However, some hardware implementations lock this bit as Read-Only because the hardware or underlying architecture does not support the functionality that this bit provides. You can continue to implement Traffic Priority as Read-Only if it best fits the capabilities of your controller.
Interrupt Generation on Completion
The Intel HD Audio Specification requires that DMA engines generate interrupts when they complete each descriptor. Along with these interrupts, the specification also defines a Buffer Completion Interrupt Status bit, as follows:
“Buffer Completion Interrupt Status (BCIS): For an outbound engine, this bit is set to 1 by the hardware after the last byte of data for the current descriptor has been fetched from memory and put into the DMA FIFO, and the current descriptor has the Interrupt On Completion (IOC) bit set.
“For an inbound engine, this bit is set to 1 by the hardware after the last byte of data for the current descriptor with an IOC bit set has been removed from the DMA FIFO and the current descriptor has the IOC bit set.
“BCIS remains active until software clears it by writing a 1 to this bit position.”
Microsoft interprets this to mean that your audio controller must generate IOC interrupts and set the BCIS bit at the same time for the same specific descriptor.
This section contains implementation guidelines for manufacturers and driver developers of hardware codecs. Cited sections come from the Intel HD Audio Specification 1.0 and from several of its associated Document Change Notifications (DCNs). For more details, see the specification and these DCNs.
Function Group Level versus Widget Level Low Power Support
The Intel HD Audio Low Power Capabilities Clarifications and Enhancements DCN HDA015-B specifies new requirements and capabilities for HD Audio codec power management. You can report support for the Low Power DCN by setting the Extended Power States Support (EPSS) bit in one of the following ways:
To report function group level support, set the EPSS bit on the codec’s audio function group. At this support level, every child widget of the function group must comply with the DCN and implement its required features.
To report widget level support, set the EPSS bit at the codec’s widget level. At this support level, a codec can choose to support the DCN on a subset of the child widgets in its audio function group.
If you implement support for the Low Power DCN in your codec, we recommend that you do so at the function group level. This allows the maximum power savings benefit that the specification provides.
For more information, see the Intel HD Audio Low Power DCN.
Keep Alive Enable
Another new capability that was introduced in the Low Power DCN is Keep Alive Enable. The Low Power DCN requires that digital converters that set the EPSS bit as described in the previous section also support Keep Alive Enable. This new capability addresses the problem in which digital audio outputs suffer a half-second to one-second loss at the beginning of a S/PDIF or HDMI stream while communication stabilizes between the PC output and the digital audio device (such as an A/V receiver).
Keep Alive Enable requires the codec to transmit a valid silent data stream over the associated digital interface for the duration that the converter is configured to enable this functionality. Your codec must transmit this data stream at the same sample rate, bit depth, and channel count at which the converter is programmed. For full implementation details for Keep Alive Enable, see the Intel HD Audio Low Power Capabilities DCN.
HDMI Capability Bit
The following DCNs to the Intel HD Audio Specification pertain to the implementation of HDMI audio on an HD Audio codec:
HDA034-A2: HDMI Content Protection and Multi-Channel Support
These DCNs redefine a reserved bit (bit 7) in the Pin Capabilities parameter as an HDMI-capable flag:
“HDMI indicates that the Pin Complex Widget supports connection to an HDMI Sink.”
Based on this description, Microsoft uses this bit to determine only whether the pin widget can support HDMI audio, not to determine support for certain implementations of HDMI audio on HD Audio codecs. Specifically, Microsoft cannot make any assumptions regarding support for other new controls, parameters, and functionality that are outlined in the HDMI DCNs for HD Audio based solely on this bit.
For more information about the HDMI capability bit for HD Audio pin complex widgets, see the HD Audio DCNs.
HDMI LPCM Consolidated Audio Descriptor (CAD)
The HDMI Content Protection and Multi-Channel Support (HDA034-A2) DCN for the Intel HD Audio Specification introduced the HDMI LPCM CAD parameter. Intel later removed this parameter in the Display Port Support and HDMI Miscellaneous Corrections (HDA036-A) DCN.
As a result, Microsoft system software does not use this parameter. HD Audio codecs that implement HDMI audio and that use the HDMI LPCM CAD parameter are valid. We recommend that you use this parameter as a vendor-defined parameter. Microsoft imposes no requirements on its behavior.
For more information about the HDMI LPCM CAD parameter, see the HD Audio HDMI DCNs.
Digital Copyright Polarity
International Electrotechnical Commission (IEC) standards require that the copyright bit that is embedded in a S/PDIF stream in a Digital Converter Control Verb have negative polarity (0) to indicate that copyright is asserted. However, the Intel HD Audio Specification gives the copyright bit positive polarity, as follows:
“COPY (Copyright): 1 indicates copyright is asserted; 0 indicates copyright is not asserted.”
Because it has become common practice in the HD Audio industry to use the IEC standard of negative polarity, we interpret negative polarity to mean that copyright is asserted and strongly recommend that you use negative polarity also.
For more information about the Copy bit and Digital Converter Control, see section 184.108.40.206 in the Intel HD Audio Specification.
Pin Configuration Default
Microsoft published a set of guidelines for setting the pin configuration default registers. These guidelines enable generic system software to correctly recognize the exact purpose of each pin widget on an HD Audio codec. To set these registers, use the guidelines in “Pin Configuration Guidelines for High Definition Audio Devices” on the WHDC Web site.
Section 220.127.116.11 of the Intel HD Audio Specification defines a pin widget’s Pin Configuration Default, as follows:
“The Configuration Default is a 32-bit register required in each Pin Widget. It is used by software as an aid in determining the configuration of jacks and devices attached to the codec. At the time the codec is first powered on, this register is internally loaded with default values indicating the typical system use of this particular pin/jack. After this initial loading, it is completely codec opaque, and its state, including any software writes into the register, must be preserved across reset events. Its state need not be preserved across power level changes.”
HD Audio System Integration Considerations
This section contains implementation guidelines for system builders, board manufacturers, and hardware codec manufacturers. Cited sections come from the Intel HD Audio Specification 1.0 and from several of its associated DCNs. For more details, see the specification and the DCNs.
Intel HD Audio solutions on portable PC platforms typically contain external amplifiers; that is, amplifiers that are external to the HD Audio codecs themselves. To save power, these external amplifiers can usually be enabled or disabled.
The Intel HD Audio Specification defines an External Amplifier Power Down (EAPD) control for pin complex widgets that can drive a pin from the HD Audio codec to the external amplifier to power it up or down. Unfortunately, this codec pin can also be used for S/PDIF input, in which case EAPD is no longer available to control an external amplifier. In this case, HD Audio solutions typically use general-purpose I/O (GPIO) ports to perform the same functionality. Custom software that the HD Audio codec vendor provides can discover the use of these GPIO ports, but system software cannot. As a result, system software does not operate properly with some audio solutions.
To alleviate these issues, you must initialize the mechanism that you use to control external amplifiers to the enabled state when the system fully powers up from any lower system power states. In addition, if the EAPD control is used to control an external amplifier, your solution must adhere to the HD Audio Specification’s requirement that a value of 1 means that the amplifier is enabled. The specification’s definition for EAPD is as follows:
“EAPD value is reflected on the EAPD pin; a 1 causes the external amplifier to power up, and a 0 causes it to power down. When the EAPD value = 1, the EAPD pin must be placed in a state appropriate to the current power state of the associated Pin Widget; i.e., the external amplifier must be powered down whenever the associated Pin Widget is put in a low power state, even though the EAPD value may remain 1. It is possible that more than one Pin Widget supports the EAPD function as indicated in bit 16 of the Pin Capabilities Parameter (Section 18.104.22.168); this would be true, for example, when external amps were supported for 4-channel output. In this case, each supporting Pin Widget must respond to this control; however, since there is only a single EAPD Pin, there is also only one logical value to set/get, and that value must be accessible, using this control, via any/all supporting Pin Widgets.”
For more information regarding external amplifiers, refer to the Intel HD Audio Specification.
Integrated digital microphones are becoming prevalent in PC audio solutions. However, at the time of this paper’s publication, the Intel HD Audio Specification does not address these device types.
Until the specification is updated to support digital microphones, Microsoft requires that these devices be exposed so that they appear identical to the classic analog microphone. Such implementations do not require any additional software intervention to operate correctly. Until a standard discovery mechanism for digital microphone device types and proprietary controls that are used to manipulate them is defined, no system software other than custom HD Audio codec vendor drivers can work correctly.
Any system-specific configuration of digital microphone implementations must be performed by system BIOS and must be preserved over HD Audio link and function group resets.
Microsoft can help review proposed designs for digital microphone implementations. For such assistance, contact email@example.com.
To save space, portable computers are beginning to use “combination jacks” that allow multifunction devices such as headsets (headphone and microphone) to be plugged in with just one cable. Such jacks have extra pins that allow both functional devices to work. If you use combination jacks on your system, you must continue to support separate jack detection for each functional device (that is, a headphone separate from a microphone) so that software can differentiate between attached multifunction devices such as headsets and single-function devices such as headphones.
These combination jacks have other logo testing considerations that are addressed in the “Windows 7 Audio Logo Changes” white paper.
Windows 7 does not use the 8254 timer hardware, which was used in earlier operating systems for PC Beep. Remember that this extra hardware is no longer necessary while you design your board.
Hardware Stream Redirection
With the introduction of jack presence detection in the Intel HD Audio Specification, system builders must now use jack presence detection for all analog audio jacks. With this new capability, system software can now determine the audio endpoint to use for streaming audio.
Because of the lack of jack-sensing capabilities on PC audio jacks, multi-output legacy audio solutions typically use analog hardware switches to switch between two different rendering devices (such as between integrated speakers and a headphone jack). This design limits the system’s ability to render independent streams on two outputs that were redirected in hardware.
To ensure a more consistent user experience and better end-user control, we recommend that legacy system audio designs be updated. Instead of using hardware switches to route audio between multiple outputs, remove such switches and integrate hardware that provides for independent streams to all outputs.
High Definition Audio Specification
DCN HDA034-A2: HDMI Content Protection and Multi-Channel Support
DCN HDA035-A: HDMI High Bit Rate Support
DCN HDA036-A: Display Port Support and HDMI Miscellaneous Corrections
DCN HDA039-A: HDMI ELD Memory Structure
DCN HDA015-B: Low Power Capabilities Clarifications and Enhancements
Pin Configuration Guidelines for High Definition Audio Devices