Figure 1.7 The architecture of a vector super computer The length of each vector register is usually fixed, say, sixty-four 64-bit component registers in a vector register in a Cray Series supercomputers. Other machines, like the Fujitsu VP2000 Series, use reconfigurable vector registers to dynamically match the register length with that of the vector operands.
In general, there are fixed numbers of vector registers and functional pipelines in a vector processor. Therefore, both resources must be reserved in advance to avoid resource conflicts between vector operations. A memory-to-memory architecture differs from a register-to-register architecture in the use of a vector stream unit to replace the vector registers. Vector operands and results are directly retrieved from the main memory in super words, say, 512 bits as in the Cyber 205.
SIMD Supercomputers In Figure 1.1b, we have shown an abstract model of a SIMD computer, having a singleinstruction stream over multiple data streams. An operational model of an SIMD computer is shown in Figure 1.8.
SIMD Machine Model: An operational model of an SIMD computer is specified by a 5-tuple:
M = <N , C , I , M , R> (1.5)
(1) N is the number of processing elements (PEs) in the machine. For
example, Illiac IV has 64 PEs and the Connection Machine CM-2 uses
(2) C is the set of instructions directly executed by the control unti(CU),